Abstract: A high voltage driver circuit for devices such as non-volatile memories, in which a low voltage driver is combined in two different ways with a high voltage driver In one, input-independent embodiment, a low voltage driver (Q7, Q8) is connected directly in parallel with a high voltage driver, thereby providing a high voltage signal path for high voltage operations and a low voltage signal path for low voltage operations. In an alternative, partially input-dependent embodiment, a low voltage driver is connected to the output of a high voltage driver (Q9, Q10), which may comprise a partial level shifter (Q1 B Q6). The output of this low voltage driver (Q9, Q10), which forms the output terminal of the entire stage, has a pull up/pull down transistor (Q11), depending on whether the partial level shifter (Q1 B Q6) is a positive or negative level shifting high voltage driver.