Abstract: An integrated voltage regulator may be provided on the bottom of a ball grid array processor package. This may be done despite the fact that conventionally integrated voltage regulator chips are too thick to fit in the area normally available between the motherboard and the ball grid array package because that area is defined by solder balls of a necessarily limited height which is conventionally believed to be too small to accommodate the integrated voltage regulator.

Abstract: Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Abstract: Some embodiments of the present invention include a circuit in a wireless transmitter or other apparatus is automatically calibrated using a calibration circuit to accommodate provide a desired characteristic such as a filter response, where the component values of the filter circuit may vary such as in an integrated circuit. In one embodiment, the calibration circuit is coupled to one or more adjustable capacitors in the filter circuit to select a capacitor value so that the filter circuit exhibits the desired filter response. In one particular embodiment, the adjustable capacitor is charged in an RC circuit for each clock cycle at power up. The value of the adjustable capacitor is changed for each clock cycle until the capacitor charges to a level greater than or equal to predetermined reference voltage.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interferer signal to reduce intermodulation distortion in the frequency band, wherein the attenuating occurs prior to anti-alias filtering of the baseband signal.

Abstract: Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Abstract: Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interferer signal to reduce intermodulation distortion in the frequency band, wherein the attenuating occurs prior to anti-alias filtering of the baseband signal.

Abstract: A circuit in a wireless transmitter or other apparatus is automatically calibrated using a calibration circuit to accommodate provide a desired characteristic such as a filter response, where the component values of the filter circuit may vary such as in an integrated circuit. In one embodiment, the calibration circuit is coupled to one or more adjustable capacitors in the filter circuit to select a capacitor value so that the filter circuit exhibits the desired filter response. In one particular embodiment, the adjustable capacitor is charged in an RC circuit for each clock cycle at power up. The value of the adjustable capacitor is changed for each clock cycle until the capacitor charges to a level greater than or equal to predetermined reference voltage. When the capacitor is charged to a predetermined reference voltage, a desired capacitance value is indicated, and the adjustable capacitor is maintained at the desired capacitance value to provide the desired filter output.