Patents by Inventor Bo-feng Wu

Bo-feng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170343
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 23, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Chi-On CHUI, Chih-Chieh YEH, Cheng-Hsien WU, Chih-Sheng CHANG, Tzu-Chiang CHEN, I-Sheng CHEN
  • Publication number: 20240141476
    Abstract: A method for manufacturing a target material is provided, including the steps of: disposing raw material powder on a substrate and melting the raw material powder by laser to form a target material layer; repeating the preceding process to allow a plurality of target material layers to form an integrated target material column; after cooling the target material column, removing the target material column from the substrate; and performing vacuum heat treatment on the target material column. Since the target material is additively manufactured and subjected to vacuum heat treatment, the target material has a finer and more uniform microstructure, thus improving the product quality.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: TAIWAN STEEL GROUP AEROSPACE ADDITIVE MANUFACTURING CORPORATION
    Inventors: William HSIEH, Bo-Chen Wu, Chii-Feng Huang, Jun-Cheng Wang
  • Publication number: 20240096388
    Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
  • Publication number: 20240097067
    Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
  • Patent number: 11923252
    Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
  • Publication number: 20090092690
    Abstract: This invention provides various products and processes such as a process of making a theaflavins enriched extract of tea having a low content of high molecular weight thearubigins which comprises extracting theaflavins from tea using ethanol to produce an extract having a high theaflavins content and a low content of high molecular weight thearubigins.
    Type: Application
    Filed: July 24, 2008
    Publication date: April 9, 2009
    Inventors: Hsiu Wei Yang, Shiming Li, Bu-xiang Sun, Ling-zhi Tang, Bo-feng Wu, Zhi-hui Wang, Zhen-peng Chen