Abstract: Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.

Abstract: A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-circuit; modifying the match expression to change the matching properties of components of the sub-circuit; and producing an information structure in a computer readable medium, where the information structure associates a graph representing a topology of the selected sub-circuit with the modified match expression. Subsequently, the information structure corresponding to the selected sub-circuit can be identified in a given circuit design.

Abstract: A computer implemented method is provided for interactive application of constraints to sub-circuits in a circuit design stored in a computer readable medium, comprising: receiving from a first designer a selection of a sub-circuit; receiving from the first designer a constraint; producing an information structure in computer readable medium that associates a graph representing a topology of the selected sub-circuit with the received constraint; using the graph to identify sub-circuit instances in the circuit design having the same topology as the selected sub-circuit; receiving from a second designer a selection of the information structure; presenting to the second designer one or more of the identified sub-circuit instances and the received constraint; and receiving from the second designer instruction as to application of the received constraint to one or more of the presented sub-circuit instances.

Abstract: In a method of determining the existence of one or more conflicts in the placement or configuration of circuit objects defining a circuit, a number of constraints is defined, each of which imposes at least one limitation on at least one circuit object. A number of constraint families is then defined, each of which includes a subset of interrelated constraints. For each of a subset of the constraint families, a determination is made if a conflict exists between the constraints thereof. If not, pairs of constraint families are defined from the plurality constraint families. For each of a subset of the pairs of constraint families, a determination is made if a conflict exists between the constraints thereof. If not, the circuit objects defining the circuit are laid out subject to the constraints.