Abstract: A high current, low dropout driver circuit is disclosed. The circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals to provide a load current to a load circuit, such as a light-emitting diode (LED), using activated ones of the plurality of devices and a control voltage. A control circuit is configured to generate the control voltage based on the load current and a reference current.

Abstract: A piecewise linear current-mode digital-to-analog converter circuit approximates an exponential output current over a range of input codes by generating linearly varying currents with different slopes of different ranges of the input codes. The piecewise linear current-mode digital-to-analog converter circuit includes a current generator circuit that generates the output current based on a reference voltage and a feedback signal. A variable resistance circuit is used to generate the feedback signal using the output current. Respective values of the reference voltage and the variable resistance circuit vary as a function of the input code.

Abstract: A high current, low dropout driver circuit is disclosed. The circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals to provide a load current to a load circuit, such as a light-emitting diode (LED), using activated ones of the plurality of devices and a control voltage. A control circuit is configured to generate the control voltage based on the load current and a reference current.

Abstract: The present disclosure describes a system with a first counter circuit, a first converter circuit, a second counter circuit, and a second converter circuit. The first counter circuit is configured to output a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator. The first converter circuit is configured to adjust an activation time of the voltage regulator based on the first count value. The second counter circuit is configured to output a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator. The second converter circuit is configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

Abstract: A high current, low dropout driver circuit is disclosed. The circuit includes a decoder configured to decode a plurality of control bits to generate a plurality of control signals, and a current source having a plurality of devices. The current source is configured to activate at least a subset of the plurality of devices using the control signals to provide a load current to a load circuit, such as a light-emitting diode (LED), using activated ones of the plurality of devices and a control voltage. A control circuit is configured to generate the control voltage based on the load current and a reference current.

Abstract: A piecewise linear current-mode digital-to-analog converter circuit approximates an exponential output current over a range of input codes by generating linearly varying currents with different slopes of different ranges of the input codes. The piecewise linear current-mode digital-to-analog converter circuit includes a current generator circuit that generates the output current based on a reference voltage and a feedback signal. A variable resistance circuit is used to generate the feedback signal using the output current. Respective values of the reference voltage and the variable resistance circuit vary as a function of the input code.

Abstract: The present disclosure describes a system with a first counter circuit, a first converter circuit, a second counter circuit, and a second converter circuit. The first counter circuit is configured to output a first count value based on a comparison between a first reference value and a switched node value of a voltage regulator. The first converter circuit is configured to adjust an activation time of the voltage regulator based on the first count value. The second counter circuit is configured to output a second count value based on a comparison between a second reference value and the switched node value of the voltage regulator. The second converter circuit is configured to adjust an amount of current drawn away from an output of the voltage regulator based on the second count value.

Abstract: A disconnect switch for a power converter is disclosed. An apparatus includes an inductor coupled between an input power supply node and a switch node, and a converter circuit configured to generate a particular voltage level on a boost node using a voltage level of the switch node. An output circuit is configured to provide the particular voltage level on the regulated power supply node using a voltage level of the boost node. In response to a determination that the regulated power supply node has been shorted to ground, the output circuit is configured isolate the boost node from the regulated power supply node. In response to a detection of a regulation event, the output circuit is configured to reduce the voltage level of the boost node to generate a reduced voltage on the regulated power supply node.

Abstract: A minimum voltage detector circuit is disclosed. The circuit includes a plurality of LED strings each having a plurality of series-coupled LEDs. The minimum voltage detector circuit is configured to detect a minimum voltage from among the plurality of LED strings, and also to perform open/short detection among the plurality of LED strings. The minimum voltage detector circuit includes a plurality of voltage comparators and correspondingly coupled replica circuits. Each of the voltage comparators includes an amplifier having a first input coupled to a cathode of a last LED of one of the plurality of LED strings, an output, and a second input coupled to the output. Each voltage comparator further includes a replica circuit coupled to the amplifier. The replica circuit is configured to maintain an output transistor of the amplifier in an active state when the amplifier is in an unbalanced state.

Abstract: A disconnect switch for a power converter is disclosed. An apparatus includes an inductor coupled between an input power supply node and a switch node, and a converter circuit configured to generate a particular voltage level on a boost node using a voltage level of the switch node. An output circuit is configured to provide the particular voltage level on the regulated power supply node using a voltage level of the boost node. In response to a determination that the regulated power supply node has been shorted to ground, the output circuit is configured isolate the boost node from the regulated power supply node. In response to a detection of a regulation event, the output circuit is configured to reduce the voltage level of the boost node to generate a reduced voltage on the regulated power supply node.

Abstract: A dual-stage boost converter is disclosed. The boost converter includes a charge pump and a boost stage. The charge pump is coupled between an input voltage source and the boost stage. The charge pump is coupled to receive the input voltage and configured to generate an intermediate voltage that is greater than the input voltage received from the input voltage source. The boost stage includes an inductor coupled to receive the intermediate voltage and is configured to generate an output voltage that is greater than or equal to the intermediate voltage.

Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.

Abstract: A dual-stage boost converter is disclosed. The boost converter includes a charge pump and a boost stage. The charge pump is coupled between an input voltage source and the boost stage. The charge pump is coupled to receive the input voltage and configured to generate an intermediate voltage that is greater than the input voltage received from the input voltage source. The boost stage includes an inductor coupled to receive the intermediate voltage and is configured to generate an output voltage that is greater than or equal to the intermediate voltage.

Abstract: A minimum voltage detector circuit is disclosed. The circuit includes a plurality of LED strings each having a plurality of series-coupled LEDs. The minimum voltage detector circuit is configured to detect a minimum voltage from among the plurality of LED strings, and also to perform open/short detection among the plurality of LED strings. The minimum voltage detector circuit includes a plurality of voltage comparators and correspondingly coupled replica circuits. Each of the voltage comparators includes an amplifier having a first input coupled to a cathode of a last LED of one of the plurality of LED strings, an output, and a second input coupled to the output. Each voltage comparator further includes a replica circuit coupled to the amplifier. The replica circuit is configured to maintain an output transistor of the amplifier in an active state when the amplifier is in an unbalanced state.

Abstract: The present disclosure is directed to a pulse frequency modulation (PFM) control method for a boost converter and apparatus for carrying out the method. A boost converter includes an inductor and a transistor coupled thereto. A control circuit is arranged to control the transistor to cause current pulsed to be sourced through the inductor. When operating in a PFM mode, the control circuit may control the timing of pulses such that, at the beginning of a specified time period, current pulses may be sourced with no spacing between successive pulses. After a desired number of pulses have been sourced, no pulses are sourced for the remainder of the specified time period. Nevertheless, the number of pulses sourced over the time period corresponds to a desired average frequency of pulses.

Abstract: A minimum voltage detector circuit is disclosed. The circuit includes a plurality of LED strings each having a plurality of series-coupled LEDs. The minimum voltage detector circuit is configured to detect a minimum voltage from among the plurality of LED strings, and also to perform open/short detection among the plurality of LED strings. The minimum voltage detector circuit includes a plurality of voltage comparators and correspondingly coupled replica circuits. Each of the voltage comparators includes an amplifier having a first input coupled to a cathode of a last LED of one of the plurality of LED strings, an output, and a second input coupled to the output. Each voltage comparator further includes a replica circuit coupled to the amplifier. The replica circuit is configured to maintain an output transistor of the amplifier in an active state when the amplifier is in an unbalanced state.

Abstract: An LED driver circuit is disclosed. The LED driver circuit includes an amplifier having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The circuit further includes first and second transistors each having respective gate terminals coupled to an output of the first amplifier. In a first mode, a first switch alternately couples a source terminal of the first transistor to the second input of the amplifier (when the pulse is asserted) and a source terminal of the second transistor to the second input (when the pulse is de-asserted). A third transistor includes a gate terminal that is coupled to ground, by a second switch, when operating in the first mode. When operating in the second mode, the switch couples the third transistor to the output of the amplifier, while the pulse remains asserted.

Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.

Abstract: A DC-DC converter providing adaptive peak current control is disclosed. A DC-DC converter includes an inductor having first and second terminals coupled to a voltage source and a transistor, respectively. The DC-DC circuit further includes a control circuit configured to control activation of the transistor. A first control block of the control circuit controls the transistor (and thus the inductor peak current) using pulse frequency modulation (PFM). A second control block controls the transistor using pulse width modulation (PWM) and PFM. In a first mode of operation, the control circuit activates the transistor, using PFM, such that the peak-to-peak current through the inductor has a fixed value. In a second mode of operation, the control circuit activates the transistor such that the peak-to-peak current through the inductor is modulated, using both PWM and PFM.

Abstract: The present disclosure is directed to a pulse frequency modulation (PFM) control method for a boost converter and apparatus for carrying out the method. A boost converter includes an inductor and a transistor coupled thereto. A control circuit is arranged to control the transistor to cause current pulsed to be sourced through the inductor. When operating in a PFM mode, the control circuit may control the timing of pulses such that, at the beginning of a specified time period, current pulses may be sourced with no spacing between successive pulses. After a desired number of pulses have been sourced, no pulses are sourced for the remainder of the specified time period. Nevertheless, the number of pulses sourced over the time period corresponds to a desired average frequency of pulses.