Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.

Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

Abstract: A method for servicing a call with a door phone includes: requesting, by a server on a network supporting interworking between the door phone and a vehicle telematics terminal, vehicle information from the vehicle telematics terminal due to a service request from a smart terminal in a home in response to an action of the door phone; receiving, at the server, the vehicle information from the vehicle telematics terminal; and providing, by the server, a call connection between the door phone and the vehicle telematics terminal based on whether or not a vehicle is being driven, as determined by the received vehicle information.

Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.

Abstract: Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line.

Abstract: A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line.

Abstract: A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.

Abstract: A terminal apparatus for connecting with a head unit of a vehicle comprises a communicator configured to perform communication with the head unit equipped in the vehicle and a vehicle center server. A storage is configured to download an application from the vehicle center server and store it. A controller is configured to check information of the head unit by executing the application and execute a user interface corresponding to the checked information.

Abstract: A method for servicing a call with a door phone includes: requesting, by a server on a network supporting interworking between the door phone and a vehicle telematics terminal, vehicle information from the vehicle telematics terminal due to a service request from a smart terminal in a home in response to an action of the door phone; receiving, at the server, the vehicle information from the vehicle telematics terminal; and providing, by the server, a call connection between the door phone and the vehicle telematics terminal based on whether or not a vehicle is being driven, as determined by the received vehicle information.

Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Abstract: A memory system includes a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Abstract: A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Abstract: A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.