Patents by Inventor Boh-Yi HUANG
Boh-Yi HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240160820Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).Type: ApplicationFiled: January 22, 2024Publication date: May 16, 2024Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
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Publication number: 20240135078Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: January 4, 2024Publication date: April 25, 2024Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Patent number: 11900035Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).Type: GrantFiled: March 1, 2023Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
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Patent number: 11900037Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: GrantFiled: May 24, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20240037302Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.Type: ApplicationFiled: August 8, 2023Publication date: February 1, 2024Inventors: Chih-yuan Stephen YU, Boh-Yi HUANG, Chao-Chun LO, Xiang GUO
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Patent number: 11783104Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.Type: GrantFiled: July 14, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-yuan Stephen Yu, Boh-Yi Huang, Chao-Chun Lo, Xiang Guo
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Publication number: 20230205958Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
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Patent number: 11620423Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).Type: GrantFiled: September 15, 2020Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
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Publication number: 20220414304Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.Type: ApplicationFiled: July 14, 2022Publication date: December 29, 2022Inventors: Chih-yuan Stephen YU, Boh-Yi HUANG, Chao-Chun LO, Xiang GUO
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Publication number: 20220284162Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Patent number: 11403448Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.Type: GrantFiled: April 23, 2021Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-yuan Stephen Yu, Boh-Yi Huang, Chao-Chun Lo, Xiang Guo
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Patent number: 11347920Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: GrantFiled: October 21, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-Yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20220121798Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
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Publication number: 20220083717Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
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Publication number: 20220012392Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Inventors: Boh-Yi Huang, Chao-Chun Lo, Chih-yuan Stephen Yu, Tze-Chiang Huang, Chen-jih Lui
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Patent number: 10540462Abstract: A method includes providing a register transfer level (RTL) description of a circuit design, providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist, providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design, capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time wherein the specified period of time is less than a time period required to compete a full-scale simulation, mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist, capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time, and simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.Type: GrantFiled: July 10, 2017Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Yuan Stephen Yu, Wenyuan Lee, Boh-Yi Huang, Brent Lui, Tze-Chiang Huang
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Publication number: 20180165394Abstract: A method includes providing a register transfer level (RTL) description of a circuit design, providing a plurality of RTL-to-gate-level mapping details by translating the RTL description into a gate-level netlist, providing one or more input/output (I/O) variables as stimulus to simulate the RTL description of the circuit design, capturing a plurality of internal operation values from the simulated RTL description at a beginning time of a specified period of time wherein the specified period of time is less than a time period required to compete a full-scale simulation, mapping the captured internal operation values to corresponding gate-level nodes of the gate-level netlist, capturing a plurality of I/O values from the I/O variables at the beginning time of the specified period of time, and simulating the circuit design in a gate-level for the specified period of time based on the mapped internal operation values and the captured I/O values.Type: ApplicationFiled: July 10, 2017Publication date: June 14, 2018Inventors: Chih-Yuan Stephen YU, Wenyuan LEE, Boh-Yi HUANG, Brent LUI, Tze-Chiang HUANG