Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.

Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and second boundaries are further positioned in accordance with an integer multiple of the first pitch when the computer is invoked to form the plurality of cells representing the circuit.

Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells. Each cell is characterized by a multitude of first shapes extending along a first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. Each cell is further characterized by a cell origin including a first cell coordinate associated with the second direction. The first cell coordinate is assigned in accordance with an integer multiple of the first pitch when the computer is invoked to form the multitude of cells representing the circuit.

Abstract: A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and second boundaries are further positioned in accordance with an integer multiple of the first pitch when the computer is invoked to form the plurality of cells representing the circuit.

Abstract: Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information.

Abstract: Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information.

Abstract: Reconstruction methods and devices are disclosed for scan chains in physical design that is based on two-way priority selection. The structural reconstruction method in the scan chains, in the first place, establishes a first preference sequence for a certain number of scanning elements in each of these scan chains as well as a secondary preference sequence for these scan chains in each of these scanning elements respectively. Then, two-way selection is executed between the scan chains and scanning elements based on the corresponding first preference sequence and secondary preference sequence, so that these scanning elements can be redistributed to these scan chains. The structural reconstruction method and device in the invention conduct an integrated optimization for a global scan chain, where the global wiring length is shortened dramatically and the wiring efficiency is improved.

Abstract: Reconstruction methods and devices are disclosed for scan chains in physical design that is based on two-way priority selection. The structural reconstruction method in the scan chains, in the first place, establishes a first preference sequence for a certain number of scanning elements in each of these scan chains as well as a secondary preference sequence for these scan chains in each of these scanning elements respectively. Then, two-way selection is executed between the scan chains and scanning elements based on the corresponding first preference sequence and secondary preference sequence, so that these scanning elements can be redistributed to these scan chains. The structural reconstruction method and device in the invention conduct an integrated optimization for a global scan chain, where the global wiring length is shortened dramatically and the wiring efficiency is improved.