Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.

Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

Abstract: Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.

Abstract: In one embodiment, an integrated circuit apparatus comprises a substrate that includes electrical contacts on a first side of the substrate to couple the substrate to an integrated circuit die, a passivation layer on a second side of the substrate opposite the first side, metal pads on the second side of the substrate and within openings defined by the passivation layer, and solder bumps on the metal pads. The solder bumps are a material that is resistant to Gallium-based liquid metal embrittlement.

Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

Abstract: Through glass via structures including via metallizations and gaps between the via metallizations and sidewalls of openings in the glass substrate, and related packages, apparatuses, and systems are discussed. Glass substrates for use in an integrated circuit package have a first surface, an opposing second surface, and an opening extending between the first and second surfaces. A sacrificial material is coated on a sidewall of the opening and a via metallization is formed within the sacrificial material. The sacrificial material is removed, leaving one or more gaps between the via metallization and the sidewall of the opening to at least partially decouple the via metallization and the glass substrate.

Abstract: Glass substrates with cavities and seedless through-glass vias (TGVs), devices and systems formed thereon, and methods of forming the same, are disclosed herein. In one example, a substrate includes a glass layer with a rectangular prism volume, a cavity in the glass layer, and one or more vias extending between top and bottom surfaces of the glass layer. The vias are filled with a first conductive material, and the sidewalls of the vias are not lined with a second conductive material.

Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Abstract: Assemblies and methods of manufacturing assemblies that include sockets and packaged semiconductor chips are provided. The package substrates for the semiconductor chips can include cores that are formed from a solid amorphous glass layer. The package substrates can have gaps around sides and alignment pins in the assemblies.

Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.

Abstract: Embodiments disclosed herein may include an apparatus that includes a substrate with a first edge surface. In an embodiment, the substrate may comprise a glass layer. In an embodiment, a via is formed through a thickness of the substrate. In an embodiment, an organic dielectric layer is provided over the substrate, and the organic dielectric layer has a second edge surface. In an embodiment, a recess is formed into the second edge surface of the organic dielectric layer.

Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.

Abstract: 3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.

Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.