Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Abstract: Assemblies and methods of manufacturing assemblies that include sockets and packaged semiconductor chips are provided. The package substrates for the semiconductor chips can include cores that are formed from a solid amorphous glass layer. The package substrates can have gaps around sides and alignment pins in the assemblies.

Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.

Abstract: Embodiments disclosed herein may include an apparatus that includes a substrate with a first edge surface. In an embodiment, the substrate may comprise a glass layer. In an embodiment, a via is formed through a thickness of the substrate. In an embodiment, an organic dielectric layer is provided over the substrate, and the organic dielectric layer has a second edge surface. In an embodiment, a recess is formed into the second edge surface of the organic dielectric layer.

Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.

Abstract: 3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.

Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.

Abstract: Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods for alleviating crack formation and propagation in glass by providing various edge features during or after singulation of a glass panel into individual glass units. In some embodiments, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge, where a material of the protection coating includes a low-density polystyrene foam, an ionogel, a fiber reinforced resin, a pre-impregnated dielectric, a pre-impregnated fabric, a carbon nanotube reinforced epoxy resin, a metal oxide, a mold material, or a solder resist.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.

Abstract: According to the various aspects, a method is provided for dicing a semiconductor panel having a glass core with topside build-up (BU) layers, backside BU layers, and interconnects. In an aspect, a hard mask is deposited on the semiconductor panel and patterned to form openings for a plurality of cut-streets. In an aspect, the dicing of the semiconductor panel includes using plasma dicing steps to form cut-streets through the topside BU layers and the backside BU layers, and using a mechanical sawing step or plasma dicing step to cut through the glass core. In another aspect, the dicing of the semiconductor panel further includes using an acid rinse to remove metal salts when cutting through the glass core during the plasma dicing step. In another aspect, a singulated die may have a first BU sidewall and a second BU sidewall having a morphology that includes semi-sphere fillers.

Abstract: Microelectronic assemblies with glass cores with tapered insulator edges, as well as related devices and fabrication techniques, are disclosed. In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face, and an insulator material having a bottom face, a top face opposite the bottom face, and an outer edge extending between the bottom face and the top face. The top bottom face of the insulator material is on the glass core, and the outer edge of the insulator material tapers from a first perimeter at the bottom face to a second perimeter at the top face. The taper of the outer edge results in the first perimeter being larger than the second perimeter.

Abstract: A packaging apparatus and methodology for a glass core package that can replace a BGA pinout with a well material perforated with through-holes filled with LM and protected by a thin layer of a dielectric material. The glass package with liquid metal (LM) socketing is to attach to a LM-compatible socket; the LM-compatible socket can be soldered to a main board or printed circuit board (PCB).

Abstract: Architectures and process flows for frames for glass core hybrid panels for semiconductor packaging. The glass core includes a layer of glass defined by a planar area enclosed by one or more edges that are substantially orthogonal to the planar area and at least one through-glass via (TGV) in the layer of glass, substantially filled with a conductive material. The frame comprises a coefficient of thermal expansion (CTE) that can be manipulated based on selection of frame material and/or percentage of copper in the frame material. The frame has a CTE of less than 11. The frame can enclose a panel, sub-panel or wafer and can include one or more cavities therein for respective glass cores.

Abstract: Thin glass cores for integrated circuit (IC) packages. Recesses in a glass core may be selectively etched into a frontside and/or backside of the glass core to locally reduce the thickness of glass. A dielectric material may be applied over the glass to backfill the recesses. The glass may then be further thinned from a same side as the recess to reduce the thickness of regions outside of the recesses. Alternatively, the glass may then be further thinned from a side of the glass opposite the recess to reduce the thickness of regions outside of the recesses and also remove the lesser thickness of glass remaining at the location of the recess. Panels comprising the thin glass core may then be built-up with routing metallization and assembled with IC die.

Abstract: Embodiments disclosed herein include an apparatus that comprises a substrate. In an embodiment, the substrate comprises a glass layer. In an embodiment, a frame is provided around a perimeter of the substrate. In an embodiment, the frame is over a top surface, a bottom surface, and a sidewall surface of the substrate. In an embodiment, the frame comprises a conductive material.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass layer, a first layer comprising a photo-imageable dielectric (PID) material above the glass layer, a second layer below the glass layer, the second layer comprising the PID material, at least one buildup layer above the first layer, and at least one buildup layer below the second layer.