Patents by Inventor Bohan YAN

Bohan YAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413137
    Abstract: Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (“die”) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Inventors: Kuiwon Kang, Joan Rey Villarba Buot, Bohan Yan, Manuel Aldrete
  • Patent number: 11749579
    Abstract: An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: September 5, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Aniket Patil, Hong Bok We, Bohan Yan
  • Patent number: 11437335
    Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Aniket Patil, Bohan Yan, Dongming He
  • Publication number: 20220278016
    Abstract: An IC package includes a heat-generating device and an electrical device on a surface of a substrate, a mold compound disposed on the electrical device, and a thermal structure disposed on the heat-generating device, without the mold compound, to improve heat dissipation. In an example, the thermal structure includes a thermal interface material (TIM) layer and a heat sink. In the example, the TIM layer extends from the heat-generating device to a height equal to or less than the mold compound and the heat sink includes a planar exterior surface above the heat-generating device and the electrical device. In an example, a first heat sink portion of the heat sink on the heat-generating device may be a different thickness than a second heat sink portion of the heat sink on the electrical device. The thermal structure reduces a thermal resistance between the heat-generating device and the heat sink.
    Type: Application
    Filed: March 1, 2021
    Publication date: September 1, 2022
    Inventors: Aniket Patil, Hong Bok We, Bohan Yan
  • Publication number: 20210249359
    Abstract: Examples herein include better heat transfer from application processor(s) and power management system without affecting the EMI performance. In one example, a thermal solution structure improves thermal performance of a modular system with better EMI shielding with the addition of heat conduction pillars from the substrate metal layer to TIM material, which thereafter connects to a heat pipe. The pillar transfers heat from substrate to heat pipe and connects physically to a global ground reference net of the IC package and eventually to a system motherboard while the pillar shields components inside the array/ring. This gives both a thermal and EMI shield solution in a single structure.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 12, 2021
    Inventors: Aniket PATIL, Bohan YAN, Hong Bok WE
  • Publication number: 20210242160
    Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation.
    Type: Application
    Filed: July 6, 2020
    Publication date: August 5, 2021
    Inventors: Kuiwon Kang, Aniket Patil, Bohan Yan, Dongming He
  • Patent number: 10679919
    Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Zhijie Wang, Bohan Yan
  • Publication number: 20190393120
    Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Kuiwon KANG, Zhijie WANG, Bohan YAN