Patents by Inventor BoHan Yoon

BoHan Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8994196
    Abstract: A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungYoon Lee, JungHoon Shin, BoHan Yoon
  • Patent number: 8035211
    Abstract: An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: October 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, BoHan Yoon, JoungUn Park
  • Publication number: 20110101546
    Abstract: A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer.
    Type: Application
    Filed: January 13, 2011
    Publication date: May 5, 2011
    Applicant: STATS CHIPPAC, LTD.
    Inventors: SungYoon Lee, JungHoon Shin, BoHan Yoon
  • Patent number: 7892072
    Abstract: A backside grinding apparatus removes semiconductor material from a surface of a semiconductor wafer. The wafer is mounted to a backing plate. The backside surface undergoes a first grinding operation in a rotational motion to remove excess semiconductor material. The semiconductor wafer is then aligned such that edges of the die are oriented along a reference line. The backside surface undergoes a second grinding operation in a linear direction on a 45-diagonal with respect to the reference line to create linear grind marks which are diagonal to the edges of the die. The linear grind marks are formed by an abrasive surface having at least 4000 mesh count. The second grinding operation removes the radial grind marks produced by the first grinding operation. The linear grind marks oriented diagonal with respect to the reference line increases the strength of the die to resist cracking.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: February 22, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SungYoon Lee, JungHoon Shin, BoHan Yoon
  • Patent number: 7659140
    Abstract: An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee, BoHan Yoon
  • Publication number: 20090243070
    Abstract: An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 1, 2009
    Inventors: WonJun Ko, BoHan Yoon, JoungUn Park
  • Publication number: 20090068933
    Abstract: A backside grinding apparatus removes semiconductor material from a surface of a semiconductor wafer. The wafer is mounted to a backing plate. The backside surface undergoes a first grinding operation in a rotational motion to remove excess semiconductor material. The semiconductor wafer is then aligned such that edges of the die are oriented along a reference line. The backside surface undergoes a second grinding operation in a linear direction on a 45-diagonal with respect to the reference line to create linear grind marks which are diagonal to the edges of the die. The linear grind marks are formed by an abrasive surface having at least 4000 mesh count. The second grinding operation removes the radial grind marks produced by the first grinding operation. The linear grind marks oriented diagonal with respect to the reference line increases the strength of the die to resist cracking.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 12, 2009
    Applicant: STATS CHIPPAC, LTD.
    Inventors: SungYoon Lee, JungHoon Shin, BoHan Yoon
  • Publication number: 20080242053
    Abstract: An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Taewoo Lee, Sang-Ho Lee, BoHan Yoon