Abstract: This document discloses semiconductor processing systems, methods, and devices. The systems, methods and devices activate dopants in a processing chamber having a temperature that is less than, for example, 300 degrees. A microwave energy source provides a microwave transmission to a waveguide system that uniformly distributes the microwave transmission. The waveguide system can include a rectangular waveguide coupled to a cylindrical waveguide. The rectangular waveguide guides the microwave transmission in a second propagation direction to a cylindrical waveguide. The cylindrical waveguide uniformly distributes the electromagnetic transmission and guides the electromagnetic transmission in a third propagation direction to a processing chamber. A semiconductor wafer can be exposed to the microwave transmission and the temperature of the chamber to activate dopants in the semiconductor wafer.

Abstract: This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.

Abstract: This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.

Abstract: This document discloses non-volatile memory cells and methods of manufacturing the same. The memory arrays are byte, word, and/or page addressable without using a byte select transistor. The byte select transistor is eliminated by using the well, memory transistor control gates, and select transistor gates to selectively program a byte, word, or page.

Abstract: This document discloses non-volatile memory cells and methods of manufacturing the same. The non-volatile memory cells are self-aligned and have a reduced tunnel window area that is within an active region of a substrate. The tunnel window area can be reduced using mask openings without optical proximity correction that define tunnels having one or more curvatures.

Abstract: Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates associated with each of the devices as a mask during formation of the respective sources and drains.

Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.

Abstract: An EEPROM having a charge storage element, i.e., a floating gate, in the substrate adjacent to vertically separated source and drain electrodes. An electrically transparent poly control gate allows relatively low voltages to be used for program, erase, and read operations when a plurality of similar devices are arranged in a memory array. A second poly member, called a tunnel poly member, communicates with source and drain electrodes in synchronism with the poly control gate to provide charge carriers to the floating gate. Manufacturing involves a series of layers with minimal needs for photolithography.

Abstract: Memory arrays can be implemented including word lines connected to memory transistors and corresponding select transistors. Each memory transistor is also connected to an array select transistor. Each select transistor is also connected to a bit line. The memory transistors are arranged such that they define bytes of data. A well line is connected to each portion of the semiconductor substrate that defines an array of bytes.

Abstract: A memory device can be implemented including word lines connected to an array of memory transistors. Each memory transistor is also connected to bit lines and a select transistor. The select transistors each have their sources connected to a conductive source line, by a shunt and the gate of each select transistor is connected to a select line.

Abstract: The subject matter of this specification can be embodied in, among other things, a method for manufacturing and a structure of a byte-addressable electrically erasable programmable read-only memory (EEPROM). In a first aspect, a byte-addressable EEPROM integrated circuit includes isolation means, in each of a plurality of memory bytes, for electrically isolating the EEPROM byte select transistor from an EEPROM memory bit disposed closest to the byte select transistor. In one example, the isolation means precludes the need to use a wide STI oxide for isolation, and thereby avoids the process variation of active area of memory bits.

Abstract: An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the Y-direction portions to define two non-volatile memory transistors in each memory cell. Memory cells are replicated in the word line direction and then mirrored with respect to the word line to form the next row or column. This geometry is contactless because the word line and source/drain regions are all linear throughout the array so that electrical contact can be established outside of the array of cells. Each transistor can be addressed and thus programmed and erased or pairs of transistors in a line can be erased, i.e.

Abstract: Biomolecules in solid or liquid form are targeted with a UV beam of about 260 nm that is attenuated by absorption in the biomolecules. The attenuated light passes through a UV transmissive window and partly discharges an underlying floating gate EPROM device. The incremental partial discharge of the floating gate device alters the threshold voltage of the device and is read by an analog output amplifier. Variation in threshold voltage of the device is measured with respect to the extent of optical absorption by the biomolecules resulting in photometric data. A biomolecule target array can be fabricated as an X-Y array in a chip or wafer over an array of correspondingly spaced EPROM devices with control devices forming cells with each cell separately readable.

Abstract: A non-volatile transistor memory array having memory cells, each with a control transistor and a floating gate memory transistor. The cells are arranged in symmetric quadrants with active regions appearing as tic-tac-toe style strips having a central shared drain erase region. Within the drain erase region is an avalanche diode that has overlying regions of four floating gates of the memory transistors and serving to supply erase current of holes and electrons to addressed floating gates. The cells have four voltage lines or contacts, including a wordline and a bitline, a common source line and a substrate contact that are used both for addressing and for controlling distributed device capacitance in a manner that treats the floating gate as one plate of a virtual capacitor, the other plate being distributed device capacitance in the control transistor, and the memory transistor including the four voltage lines or contacts.

Abstract: A method of fabricating structures in an electronic device by forming and patterning a first film layer on a substrate into ridges with a photolithographic system. The ridges are formed from an image produced by a first simple geometry photomask where the first photomask has at least one first slot-like feature. The ridges are patterned into the structures which are essentially rectangular in shape and formed from an image produced by a second simple geometry photomask. The second photomask has at least one second slot-like feature arranged substantially orthogonal to the at least one first slot-like feature on the first photomask. The structures each have at least one dimension less than a limit-of-resolution of the photolithographic system where the dimension is measured in a plane substantially parallel to a face of the substrate.

Abstract: An electrically programmable memory cell and corresponding method for fabricating the same, provide a reduced electron tunneling threshold to reduce parasitic substrate currents during cell programming. A floating gate of the cell is formed over an injector dopant region diffused within and encompassed by a first dopant region. Both dopant regions are situated beneath a self-aligned tunneling window of the floating gate. The dopant regions are each high concentration dopants and of complementary species to one another. The injector dopant region produces an increase in surface potential that lowers a tunneling barrier height and produces the lower electron tunneling threshold.

Abstract: A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Abstract: A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Abstract: Bit lines in a memory array are configured by a select switch matrix to apply the same VD voltage to two adjacent bit lines on the drain side of a selected memory cell for the purpose of blocking charge leakage through the cell adjacent to the selected or addressed cell. The switch matrix features transistors with electrodes connected to bit line segments while control electrodes are connected to control lines from a select decoder. The switch matrix communicates with address decoders for setting switches needed to configure the bit lines as needed with the charge leakage blocking voltage.

Abstract: Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.