Abstract: A MOS transistor having utility as a charge storage device, as in a nonvolatile memory device, or as an amplifier, using the charge storage feature of the device as a way to modulate the conductivity of a channel between source and drain electrodes. Over a doped substrate, a gate oxide layer isolates a doped, electrically isolated, charge reservoir layer from the substrate. An overlying tunnel barrier layer isolates the charge reservoir layer from a nanocrystal layer capable of receiving or dispensing electric charge to the charge reservoir layer under the influence of a control gate overlying the nanocrystal layer and separated by an oxide layer. Electric charge on the charge reservoir layer influences the conductivity of the channel. The device may be operated in a memory mode, like an EEPROM, or in an amplifier mode where changes in the gate voltage are reflected in conductivity changes of the channel.

Abstract: A tiny tunnel oxide window with dimensions smaller than the minimum feature resolution of the process equipment is formed in an EEPROM structure by placing dummy nitride spacers on either side of a nitride implant mask over a gate oxide layer after source and drain are formed by implantation at opposed sides of the nitride mask. The spacers are formed in a second nitride layer deposit after the nitride mask formation. The spacers are etched to have a desired tunnel oxide dimension. Another oxide layer is deposited over one of the source and drain regions, abutting a nitride spacer. The nitride layers are removed leaving a spacer nest, into which tunnel oxide is deposited. The device is finished in the usual way for an ESPROM structure.

Abstract: Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: A method for preventing thermal stress and the shifting of alignment marks during semiconductor processing including providing a semiconductor wafer having a first selected portion for fabricating integrated circuitry and a second non-fabrication portion including alignment marks, introducing dopant into said first and second portions, when dopant is required to be introduced in said first portion, thereby increasing radiant energy absorptivity and decreasing radiant energy transmissivity in both portions such that the thermal emissions detected.at the portions result in no significant temperature variation between portions during heating. Therefore thermal stress and shifting of alignment marks are prevented.

Abstract: Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: A nonvolatile memory cell is constructed with a charge transfer window have a charge transfer region smaller than the minimum resolution feature size of used to construct the cell. The window is constructed to the minimum feature size, but its layout position places it partly within the channel region of the cell and partly within a field oxide barrier wall. The part of the window that lies within the channel region does not reach across the width of the channel to an apposing field oxide barrier wall and does not reach along the length of the channel region to either of opposedly laid source and drain regions. The oxide within the window is evenly etched back to reveal the substrate within the channel region. A thin tunneling oxide is then grown within the window, including the part of the window encompassing the field oxide barrier wall.

Abstract: Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: A nonvolatile memory cell is constructed with a charge transfer window have a charge transfer region smaller than the minimum resolution feature size of used to construct the cell. The window is constructed to the minimum feature size, but its layout position places it partly within the channel region of the cell and partly within a field oxide barrier wall. The part of the window that lies within the channel region does not reach across the width of the channel to an apposing field oxide barrier wall and does not reach along the length of the channel region to either of opposedly laid source and drain regions. The oxide within the window is evenly etched back to reveal the substrate within the channel region. A thin tunneling oxide is then grown within the window, including the part of the window encompassing the field oxide barrier wall.

Abstract: Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: A nonvolatile memory cell is constructed with a charge transfer window have a charge transfer region smaller than the minimum resolution feature size of used to construct the cell. The window is constructed to the minimum feature size, but its layout position places it partly within the channel region of the cell and partly within a field oxide barrier wall. The part of the window that lies within the channel region does not reach across the width of the channel to an apposing field oxide barrier wall and does not reach along the length of the channel region to either of opposedly laid source and drain regions. The oxide within the window is evenly etched back to reveal the substrate within the channel region. A thin tunneling oxide is then grown within the window, including the part of the window encompassing the field oxide barrier wall.

Abstract: The present invention relates to a method of forming a non-volatile memory device such as an EEPROM device. The non-volatile memory device is formed of an array of memory cells (10) organized into rows (20) and columns (22) within a semiconductor substrate (100). Each cell (10) comprises a gate structure (120) formed of a first dielectric layer (122), a floating gate (124), a second dielectric layer (126) and a control gate (128) formed in a well (50). The memory device further comprises insulating trenches (200) formed in said substrate (100) along a direction parallel to said columns (22) and isolating each cell (10) within a column (22) from other cells (10) within adjacent columns (22).

Abstract: The present invention relates to a method of forming a non-volatile memory device such as an EEPROM device. The non-volatile memory device is formed of an array of memory cells (10) organized into rows (20) and columns (22) within a semiconductor substrate (100). Each cell (10) comprises a gate structure (120) formed of a first dielectric layer (122), a floating gate (124), a second dielectric layer (126) and a control gate (128) formed in a well (50). The memory device further comprises insulating trenches (200) formed in said substrate (100) along a direction parallel to said columns (22) and isolating each cell (10) within a column (22) from other cells (10) within adjacent columns (22).

Abstract: A semiconductor structure is provided having an improved oxide with minimal irregularities and charge trap densities. The oxide is formed by an oxidation process which controls temperature and ambient conditions during oxidation as well as prior to and after oxidation. The ambient conditions are chosen such that the silicon surface is more receptive to growing a high quality, relatively thin oxide. A post-oxidation anneal helps ensure any irregularities, dislocations, contaminants involved in trap formation are minimized after the oxide is grown. A post-oxidation anneal involving oxygen incorporated into the oxide is presumed to help minimize any defects which might result from the pre-existing oxidation cycle. A slow ramping of temperature and close control of that temperature helps minimize trap locations at or near the silicon surface on which oxide will be grown.

Abstract: Dopants from a diffusion source (16) are diffused into a product wafer (14) to form a uniform doping concentration within the product wafer (14). The source (16) has a thermal conductivity that is approximately equal to a thermal conductivity of the wafer (14). The source (16) is positioned near the wafer (14) thereby forming a space (23) between the source (16) and the wafer (14). Gas flow (26) through the space (23) is limited to a predetermined value in order to prevent disturbing dopant diffusion. The source (16) is heated to a predetermined temperature, then the wafer (14) is heated. Subsequently, the wafer (14) and the source (16) are cooled at substantially equal rates.