Abstract: A method for simplifying common mode feedback circuitry utilized in multi-stage operational amplifiers may comprise generating a first differential output signal by a first amplifying circuit in an amplifying stage and communicating the first differential output signal to a first output of the amplifying stage. A second amplifying circuit in the amplifying stage may generate a second differential output signal that may be communicated to a second output of the amplifying stage. The second differential output signal may be fed back to a first feedback circuit in the amplifying stage, and the first differential output signal may be fed back to a second feedback circuit in the amplifying stage. Additionally, the first and the second differential output signals may be fed back to the second feedback circuit and the first feedback circuit, respectively, in a first amplifying stage and/or any one or more of succeeding amplifying stages.

Abstract: Embodiments of the present invention provide an oscillator circuit having a steady output frequency that is independent of the supplied voltage. This oscillator includes a Schmitt trigger circuit which may be implemented within an integrated circuit of a wireless terminal or other like portable electronic device. The Schmitt trigger circuit receives a threshold voltage input and a second voltage input. The Schmitt trigger circuit generates an output voltage equal to either a first output voltage or a second output voltage based on the results of comparing the threshold voltage input to the second voltage input. An RC network may be coupled to the output of the Schmitt trigger circuit and is operable to supply the second voltage input to the Schmitt trigger circuit.

Abstract: Aspects of a method and system for FM communication are provided. An FM transceiver may generate FM radio frequency signals for transmission by modulating a single PLL within the FM transceiver via at least one modulation point with a frequency modulated multiplexed audio signal. The single PLL may also generate signals for downconversion of FM radio signals received by the transceiver. The single PLL may be modulated via a first modulation point in a feedback loop in the single PLL. In some instances, a reference frequency path within the single PLL may be selected to achieve the appropriate loop bandwidth for generating the FM radio signal for transmission. A second modulation point may be achieved by adding the modulated multiplexed audio signal to an input of a VCO within the single PLL. Moreover, the single PLL may be modulated via the first and second modulation points concurrently.

Abstract: An apparatus and method for allowing two different signal paths to be coupled to a multi-tap transformer balun. The multi-tap transformer has a first port, which is coupled to a single antenna, and two or more differential secondary ports. Each port has one or more taps, which are optimized separately for each of the signal paths, allowing each of the two or more signal paths to operate in different frequency bands. Use of the method of the invention can decrease the number of external components and integrated circuit package pins, and reduce the area required for each signal path on an integrated circuit die, a printed circuit board, or the like.

Abstract: A method and system sharing a Bluetooth processor for FM functions are provided. The single chip may comprise an integrated Bluetooth radio, an integrated FM radio, and processor system. A processor in the processor system may be utilized for Bluetooth and FM data processing and may time multiplex between the Bluetooth and FM data processing based on interrupt signals. The processor may operate in a low power mode based on a clock signal generated from a low power oscillator. When a Bluetooth interrupt signal is received, the processor may enable Bluetooth data processing that may be based on a Bluetooth clock signal. When an FM interrupt signal is received, the processor may enable FM data processing that may be based on an FM clock signal. When data processing is complete, the processor may return to the low power mode operation.

Abstract: A method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor are provided. The single chip may comprise a Bluetooth radio, an FM radio, a processor system, and a peripheral transport unit (PTU). FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. The FM radio may receive radio data system (RDS) data. The PTU may support digital and analog interfaces. A processor in the processor system may time-multiplex processing of FM data and processing of Bluetooth data. The single chip may operate in an FM-only, a Bluetooth-only, and an FM-Bluetooth mode. The single chip may reduce power consumption by disabling portions of the Bluetooth radio during FM-only mode and/or disabling analog circuitry when performing digital processing. Communication between Bluetooth and FM channels may be enabled via the single chip.

Abstract: A method and system for flexible FM tuning are provided and may include tuning to a particular frequency within a range of FM channels based on an IF frequency that includes an integer multiple of the channel spacing between neighboring allocated FM channels within the range of FM channels, offset by at most one-half the channel spacing. The method may further include determining whether the particular frequency comprises an on frequency channel, utilizing a frequency error that is based on the IF frequency. A local oscillator frequency may be selected for the tuning based on the frequency offset. An intermediate frequency (IF) channel may be generated utilizing the particular frequency and the selected local oscillator frequency. The generated IF channel may be between neighboring channels selected from the range of FM channels. The frequency error may be determined for the particular frequency within the range of FM channels.

Abstract: A complex filter such as the channel select filter in a radio transceiver is implemented using a transconductance/C topology to benefit from the ability to tune such filters and thereby stabilize the output transfer function of the filter over variations in temperature, power supply voltage and process. The topology is based on an active R/C biquadratic topology to achieve the additional benefit of independently controlled stages. The problem created by the R in the output impedance is can be overcome by separately tuning the R value along with the transconductance/C ratio, by implementing the R as a transconductance amplifier having common mode feedback, or by implementing the transconductance amplifiers of the topology using Nauta transconductors, and unbalancing the common mode circuit of the Nauta transconductor to achieve a differential resistance that can be used to implement the R in the output impedance.

Abstract: A chip comprises and operational section and an input/output section. The operational section includes a controller. The input/output (I/O) section is coupled to the operational section. The I/O section comprises a transformer and a switching device. The transformer includes a primary side connected to first and second I/O ports and a secondary side connected to the operational section. The switching device is coupled to the controller and between the first and second I/O ports and a bias port, such that, under control of the controller, the switching device connects one of the first and second I/O ports to the bias port.

Abstract: A method for simplifying common mode feedback circuitry utilized in multi-stage operational amplifiers may comprise generating a first differential output signal by a first amplifying circuit in an amplifying stage and communicating the first differential output signal to a first output of the amplifying stage. A second amplifying circuit in the amplifying stage may generate a second differential output signal that may be communicated to a second output of the amplifying stage. The second differential output signal may be fed back to a first feedback circuit in the amplifying stage, and the first differential output signal may be fed back to a second feedback circuit in the amplifying stage. Additionally, the first and the second differential output signals may be fed back to the second feedback circuit and the first feedback circuit, respectively, in a first amplifying stage and/or any one or more of succeeding amplifying stages.

Abstract: An ESD protection circuit for a transistor having a drain and source coupled to high-speed signaling pins of an integrated circuit includes a first string of clamping elements and a second string of clamping elements. The first string of clamping elements has a collective capacitance less than the capacitance of a single clamping element. The first string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a first polarity ESD voltage is applied to the high-speed pins. The second string of clamping elements has a collective capacitance less than the capacitance of one clamping element. The second string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a second polarity ESD voltage is applied to the high speed signaling pins.

Abstract: A power amplifier for use in a transmitter enables linear in dB output power control capability with 2 dB step sizes.

Abstract: The system and method enable simpler analog processing by reducing the number of bits in a digital signal through delta sigma modulation.

Abstract: A method for calibrating a frequency device by monitoring its output cycles over a first plurality of monitoring windows is disclosed. An accumulation of these monitored cycles is used to determine a correction for the device over a second plurality of monitoring windows. A method for obtaining fractional correction values to be applied for controlling the frequency device is also disclosed.

Abstract: A power-on reset circuit with glitch sensing capabilities is formed as part of the same integrated circuit chip containing other logical circuits. A port included in the integrated circuit chip enables a power-on reset signal generated by the integrated power-on reset circuit to be output from the chip and applied to other chips installed in a single chip or multi-chip electronic system. The power-on reset circuit compares a capacitor stored reset voltage to a reference voltage and outputs the power-on reset signal when the reset voltage falls below the reference voltage. Storage of the reset voltage by the capacitor is controlled by a glitch sensor which detects changes in voltage provided by a power supply in excess of a given threshold and, in response thereto, triggers a capacitor discharge. This causes the reset voltage to fall below the reference voltage, and the power-on reset signal to be output.

Abstract: A monolithic high frequency voltage controlled oscillator trimming circuit includes a plurality of capacitance loops selectively connected between a first and second differential input of a voltage oscillator active network. A plurality of diodes, connected in series with the respective plurality of capacitance loops, selectively connect respective capacitance loops between the first and second differential input when forward biased. In a similar fashion, the plurality of diodes selectively disconnect the respective capacitance loops from the first and second differential input when reverse biased. A controller applies a forward biasing voltage to the diode of the selected capacitance loop to connect the capacitance loop to the active network of the voltage controlled oscillator and applies a reverse biasing voltage to the diode of the selected capacitance loop to disconnect the capacitance loop from the active network.