Abstract: A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in the column direction, I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks and a reset sele

Abstract: An internal clock generator comprises delay units adapted and configured to delay a first clock outputted from a clock buffer for predetermined delay times to output a plurality of second clocks, respectively, clock pulse generating units adapted and configured to generate clock pulses depending on the plurality of second clocks, respectively and a clock synthesizer adapted and configured to synthesize the clock pulses to generate an internal clock. As a result, a clock frequency of test equipment is internally increased at a wafer level test mode, thereby performing a high-speed test and reducing a test cost.

Abstract: There is provided a semiconductor memory device capable of reducing power consumption by preventing unnecessary operations of an AL flip-flop delay unit and a CL flip-flop delay unit. The semiconductor memory device includes an internal column address generation means for receiving an external column address and generating an internal column address; a delay means for delaying the internal column address for a predetermined time corresponding to a preset latency; and a driving control means for driving the delay means for the predetermined time corresponding to the preset latency.