Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed. The data pins of odd-numbered packages and even-numbered packages connect to the first bus and the second bus, respectively. The control signal pins connect to the third bus. Each package can optionally include dummy pins, where the dummy pins of the even-numbered packages and the odd-numbered packages respectively connect to the first and second buses so that each of the first, second and third buses connects to the same number of external pins. The pin assignment of the even-numbered packages can be different from the pin assignment of the odd-numbered packages to facilitate connections of the buses.

Abstract: A multi in-line module and an electronic component socket for the multi in-line module are provided. One embodiment of a multi in-line memory module includes a printed circuit board having at least two protrusions formed along one edge of the printed circuit board. Each of the protrusions has first and second surfaces for blocks of contact pins. Accordingly, the module can include three or more pin blocks on separate surfaces of the protrusions. The module provides a large number of pins without being significantly larger than a conventional SIMM or DIMM. Alternatively, physical and electrical attachment of multiple circuit boards provides three or more independent pin blocks on the various surfaces of the printed circuit boards. A socket for a module includes dielectric protrusions with two or more gaps between the protrusions and contact pins on side surfaces of the protrusions that are in the gaps.

Abstract: An internal power supply circuit for a semiconductor memory device comprising a differential amplifier having a reference voltage as an input and utilizing an external power supply voltage. An amplifier output provides an internal power supply voltage. The amplifier is connected to a current source which comprises a plurality of transistors connected in series between one side of said amplifier and ground. A current control transistor having a channel larger than the channels of the transistors connected in series is switchable between a first state in which the current control transistor is substantially on and a second state in which said current control transistor is substantially off.

Abstract: A data in/out channel control circuit for a semiconductor memory device with multi-bank structure includes a plurality of split banks each provided with memory cell arrays, each split bank having a plurality of bit line pairs and a sub in/out line pair connected through a column selection transistor pair, for efficiently connecting data from the bit line pairs to a global in/out line pair. The circuit enables transmission of only the data in a given block bank through the global in/out line pair and the sub in/out line pairs with bank selection information and block selection information.

Abstract: An address buffer for a semiconductor memory device having an address input buffer and an address predecoder incorporated together so as to be driven in a single channel, capable of reducing an address predecoding time by a logic combination of outputs of address input buffer, for high speed of operation of a memory device.

Abstract: A substrate bias voltage controlling circuit controls the generation of different substrate bias voltages according to specific modes. A first sensing signal generator is controlled by the substrate bias voltage and generates a first sensing signal when the level of the substrate bias voltage is higher than a predetermined first potential level. A second sensing signal generator is controlled by the substrate bias voltage and a specific mode signal and generates a second sensing signal when the level of the substrate bias voltage is higher than a predetermined second potential level and when the mode signal is enabled.

Abstract: A low power semiconductor memory device for minimizing power consumption is disclosed. The low power semiconductor memory device includes a memory cell array with a plurality of memory cells connected to a pair of bit lines, and having first and second pairs of data lines each having a normal data line and a complementary data line. The device further includes a first switching circuit for switch-connecting the pair of bit lines to the first pair of data lines in response to column select information and a sense amplifier connected to the pair of bit lines within the memory cell array. A driving circuit transfers external data to one of the normal data line and the complementary data line of the second pair of data lines in response to a write master signal.

Abstract: Disclosed is a DC voltage generating circuit for reducing an electric power consumption in a semiconductor memory device. The DC voltage generating circuit comprises: a refresh counter for setting a refresh cycle; a power source supply controller for logically combining a counting value supplied from the refresh counter and a self-refresh timer driving signal, thereby to generate a power source supply control signal in a refresh section; and a DC voltage generator for generating and supplying a DC voltage through an output terminal of the DC voltage generator, as controlled by the power source supply control signal supplied from the power source supply controller.