Abstract: Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.

Abstract: Provided herein is an MV DRAM device for storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, where the gate of the transistor is connected to the ground voltage.

Abstract: Provided herein is an MV DRAM device capable of storing multiple value levels using an SET device. The device includes one or more word lines; one or more bitlines; a DRAM cell connected to intersections of the word lines and the bitlines; a current source transistor having a source connected to a power supply voltage and a gate and a drain connected to the bitlines; an SET (single electron transistor) device having a gate connected to the bitlines and a source connected to the ground voltage; and a transistor connected between the bitlines and the drain of the SET device, wherein the gate of the transistor is connected to the ground voltage. According to the MV DRAM device of the present invention, since two or more multiple value data are stored in a cell, it is possible to increase the storage density of the device.

Abstract: Provided is a multi-valued dynamic random access memory (DRAM) cell using a single electron transistor (SET). The multi-valued DRAM cell using the SET applies different refresh signals to a load current transistor for controlling current supply to the SET and a voltage control transistor for controlling a terminal voltage of the SET and refreshes a data value stored in the SET by a predetermined period to reduce standby current and stably supply a voltage low enough to satisfy a coulomb-blockade condition to the terminal of the SET.

Abstract: A method of erasing a flash memory in accordance with the present invention comprises: pre-programming to allow all memory cells to have the same threshold voltage; pre-programming verification for verifying whether the pre-programming is successfully executed; erasing memory cells; erasing verification for verifying whether said erasing is successfully executed; recovering over-erased cells, wherein the recovering step is performed under multiple voltages are sequentially applied to the substrate of the over-erased memory cells; and recovery verification for verifying whether the recovery step is successfully executed.

Abstract: A method for maintaining a set temperature of wash water of clothes washer comprises the steps of supplying first cold water into a wash tub, measuring supply time of the first cold water until filling a first target level of the first cold water, measuring temperature of the cold water contained in the wash tub, supplying hot water and second cold water in the wash tub containing the first cold water, measuring supply time of the hot water and the second cold water until filling a second target level of the hot water and the second cold water, measuring temperature of mixed water being comprised of the hot water and the first and second cold water contained in the wash tub, and comparing temperature of the hot water which is calculated on the following four values-supply time of the first cold water, temperature of the first cold water, supply time of the hot water and the second cold water, and temperature of the mixed water with predetermined temperature, and controlling a valve for the cold water and a va

Abstract: The present invention discloses an erasure method which can minimize a flow of current from a drain region into a substrate due to a strong electric field formed between the drain region and the substrate when a flash memory device is erased. The first erasure operation is performed in condition that a voltage of -13V is applied to a control gate and a drain and source regions are grounded, and the second erasure operation is then performed in condition that a voltage of -13V is applied to the control gate, a voltage of 5V is applied to the drain region and the source region is floated.

Abstract: The present invention relates to a flash EEPROM cell, method of manufacturing the same, and method of programming and reading the same and, more particularly, to a flash EEPROM cell constructed in such a way that two floating gates are formed on top of a channel region to implement a memory cell to, and from, which 4-numeration information can be programmed and read out, and an output of 4-numeration information is obtained depending on the programming or erasing of each of the two floating gates.

Abstract: Disclosed is a method of detecting the clogging of a filter installed in a washing machine by which a user can recognize the clogging of the filter. The method comprises the steps of detecting a first frequency using a liquid level sensor when a liquid level in an outer tub has reached a first liquid level, of recording a value of the first frequency in a memory section of the microcomputer, of demoting a second frequency using the liquid level sensor when a liquid level in the outer tub has reached a second liquid level which is formed in the outer tub while the washing cycle is being executed, of recording a value of the second frequency in the memory section of the microcomputer, of calculating a value of a third frequency by subtracting the value of the first frequency from the value of the second frequency, and of sending an operating signal to a signal lamp when the value of the third frequency is lower than a predetermined frequency range which is preset in the microcomputer.

Abstract: This invention relates to a threshold voltage verification circuit of a non-volatile memory cell which can automatically verify a threshold voltage of the cell according to the change of electron charge which is injected to a floating gate of the cell in program operation and erasure operation for the cell.