Patents by Inventor Bok-Won Cho

Bok-Won Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6319769
    Abstract: The present invention relates to a capacitor in a semiconductor device and a fabricating method thereof. More particularly, the invention relates to a method of forming a storage electrode of a capacitor in a semiconductor device and a fabricating method thereof which provide a sufficient electric charge capacitance for a highly-integrated memory device and which reduces the step difference between cell and peripheral areas. In preferred embodiments, the storage electrode has a plurality of hemispherical protruding parts, and an electrically conductive layer formed on the protruding parts. The electrically conductive layer prevents the formation of an oxide layer between the storage electrode and a dielectric layer formed over the storage electrode.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: November 20, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Bok-Won Cho
  • Patent number: 6238964
    Abstract: The present invention relates to a capacitor in a semiconductor device and a fabricating method thereof, more particularly, to an upper electrode of a capacitor and a fabricating method thereof which reduce leakage current and secure the stable thickness of the upper electrode of a three-dimensional capacitor by inserting an extra TiN layer free from Cl at an interface between an upper electrode and a dielectric layer in a capacitor, of which dielectric layer is made of Ta2O5 and of which upper electrode is made of TiN, for a semiconductor memory device. The present invention includes a lower electrode on a predetermined portion of a semiconductor substrate, a dielectric layer on a surface of the lower electrode, a first upper electrode on a surface of the dielectric layer wherein the first upper electrode consists of a substance maintaining the dielectric layer intact, and a second upper electrode on the first upper electrode.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: May 29, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Bok-Won Cho
  • Patent number: 5893980
    Abstract: A semiconductor device capacitor fabrication method comprises forming a first insulation film on a substrate and an undoped semiconductor layer on the first insulation film, patterning the undoped semiconductor layer to a desired shape, forming a second insulation film on the undoped semiconductor layer, forming contact holes by selectively etching the second insulation film, the undoped semiconductor layer and the first insulation respectively for exposing a portion of the undoped semiconductor layer therethrough, forming a first electrode film on the bottom of each of the contact holes, the undoped semiconductor layer and side walls of the second insulation film, removing the second insulation film, and forming a dielectric thin film and a second electrode film sequentially on the first electrode film. The fabrication method realizes a high dielectric constant in a large scale integration semiconductor memory device by employing new materials for a dielectric thin film and an electrode.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: April 13, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Bok-Won Cho
  • Patent number: 5817555
    Abstract: A method for fabricating a capacitor of a semiconductor device, including the steps of: sequentially forming first and second insulating layers on a substrate; selectively etching the second insulating layer to form a first contact; forming a third insulating layer on the second insulating layer including the first contact; etching the third insulating layer placed on a capacitor region including the first contact, to expose the first contact, the first contact including the second insulating layer on the capacitor region; etching the first insulating layer placed in the first contact; forming a first conductive layer on the capacitor region and third insulating layer; forming a temporary layer on the first conductive layer placed on the capacitor region; etching the first conductive layer placed on the third insulating layer using the temporary layer as a mask; removing the temporary layer, and forming a dielectric layer on the surface of the first conductive layer; and forming a second conductive layer on t
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: October 6, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Bok-Won Cho