Abstract: Disclosed are methods and devices in a battery powered electronic device (202) for hot swapping batteries, the battery powered electronic device having a battery holder (210) with a first connector (203) and a second connector (205), and having a first battery (204) in contact with both the first connector (203) and the second connector (205). The method includes maintaining power to the device from a first battery (706). The method also includes partially moving the first battery out of the battery holder in a predetermined direction to break contact with the first connector (712) while maintaining contact with the second connector (714). The method further includes partially inserting a second battery into the battery holder in the predetermined direction so that the second battery is received by the battery holder and makes contact with the first connector (712). In another embodiment the method includes charging one or another battery through the first connector or the second connector.

Abstract: A method of synchronizing enablement of a common clock for a main and a second processor in an electronic device having a low-power mode includes a first step of completing a communication activity by the main processor. A next step includes monitoring a clock enable signal from the second processor. A next step includes comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the clock enabled in the monitoring step. A next step includes calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor. A next step includes powering up and powering down the second processor under control by the main processor to synchronize the periodic timing of the second processor to that of the main processor.

Abstract: A method of synchronizing enablement of a common clock for a main and a second processor in an electronic device having a low-power mode includes a first step of completing a communication activity by the main processor. A next step includes monitoring a clock enable signal from the second processor. A next step includes comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the clock enabled in the monitoring step. A next step includes calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor. A next step includes powering up and powering down the second processor under control by the main processor to synchronize the periodic timing of the second processor to that of the main processor.