Abstract: An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.

Abstract: An image sensor includes a first pixel; a second pixel disposed adjacent to the first pixel; a pixel isolation structure disposed between the first pixel and the second pixel; a rear side anti-reflective layer disposed on the first pixel, the second pixel, and the pixel isolation structure; and a fence disposed on the rear side anti-reflective layer aligning with the pixel isolation structure and including a buried air gap.

Abstract: An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.