Abstract: A self-adaptive computer memory address allocation apparatus and method for detecting the presence of memory chips connected to predetermined memory banks of a plurality of memory modules in a computer system, receiving and remapping address signals, and contiguously enabling the predetermined memory banks in response thereto. A programmable logic array generates enable signals for enabling the predetermined memory banks of the memory modules in response to receiving address and control signals from a main controller. The remapping process is performed during power up such that no wait states are introduced during subsequent memory accesses.