Patents by Inventor Bomsoo Kim

Bomsoo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9653551
    Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changwoo Oh, Myung Gil Kang, Bomsoo Kim, Jongshik Yoon
  • Publication number: 20170053825
    Abstract: A method for manufacturing a semiconductor device includes forming a first active pattern in a first region of a substrate and a second active pattern in a second region of the substrate, wherein the first and second active patterns project from the substrate, forming a second liner pattern on the substrate and the second active pattern in the second region, wherein the second liner pattern has a second polarity, forming a first liner pattern on the substrate and the first active pattern in the first region, wherein the first liner pattern has a first polarity different from the second polarity, forming an isolation pattern on the first liner pattern in the first region and the second liner pattern in the second region, and exposing the first active pattern and the second active pattern by recessing the isolation pattern.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: KANG-ILL SEO, BOMSOO KIM, JI-HOON CHA
  • Patent number: 9525036
    Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: December 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Il Bae, Bomsoo Kim, Yong-Min Cho
  • Publication number: 20160276449
    Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin 7and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 22, 2016
    Inventors: DONG-IL BAE, Bomsoo KIM, Yong-Min CHO
  • Publication number: 20160181366
    Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 23, 2016
    Inventors: CHANGWOO OH, MYUNG GIL KANG, BOMSOO KIM, JONGSHIK YOON
  • Publication number: 20130249003
    Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fm portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 26, 2013
    Inventors: Changwoo Oh, Myung Gil Kang, Bomsoo Kim, Jongshik Yoon
  • Patent number: RE49525
    Abstract: An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction. A first recess is disposed on a sidewall of the fin so that the fin and the first recess is arranged in a straight line along the lengthwise direction. A gate structure crosses the fin in the first direction crossing the lengthwise direction. A spacer is disposed on sidewalk of the gate structure. A source/drain region is disposed in the first recess. The source/drain region is formed under the spacer. A silicide layer is disposed on the source/drain region. The silicide layer and the source/drain region fill the first recess.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Il Bae, Bomsoo Kim, Yong-Min Cho