Abstract: A method of forming a semiconductor device is provided. The method may include patterning a bottom gate area in a poly-silicon carbide (pSiC) substrate, depositing gate material in the bottom gate area to form a bottom gate terminal, planarizing the gate material, bonding a gallium nitride (GaN) wafer to the pSiC substrate, and forming a source terminal, a drain terminal, and a top gate terminal in the GaN wafer.

Abstract: A monitoring system is disclosed. The monitoring system includes a sensor and a piezoelectric speaker. The monitoring system also includes a control circuit. The control circuit is configured to drive the piezoelectric speaker to produce acoustic waves within a human-audible frequency range in response to the sensor. The control circuit is also configured to drive the piezoelectric speaker to produce ultrasonic acoustic waves that simultaneously vibrate the sensor and convey a monitoring-network signal.

Abstract: A system and method for predicting when a memory cell is idle and scheduling testing of the memory cell during an idle period are disclosed. The method may include identifying a predicted time when a memory cell is idle. The method may also include scheduling a test of the memory cell at a schedule time during the predicted time. The method may additionally include performing the test of the memory cell at the scheduled time. The method may include calculating a health score for the memory cell based on the test. The method may further include diagnosing the memory cell based on the health score.

Abstract: A nanomagnetic sticker is disclosed. The nanomagnetic sticker includes a base layer and an adhesive layer located on a first side of the base layer. The nanomagnetic sticker also includes a print layer located on a second side of the base layer, the print layer comprising patterned ink. The nanomagnetic sticker further includes a plurality of nanomagnetic particles embedded in at least one of the adhesive layer and the patterned ink.

Abstract: An integrated circuit device includes a first conductive contact to be conductively coupled to a first memory component and a second memory component of a plurality of memory components in a computing system, a second conductive contact to be conductively coupled to a first processing unit in the computing system, a memory controller circuit, and an embedded processor. The memory controller circuit is to cause first executable instructions received from the first processing unit to be stored in the first memory component and to cause the computing system to transition from a first power state to a second power state. During the second power state the second memory component and the first processing unit are to be powered down and the first memory component is to be powered up. The embedded processor is to execute the first executable instructions stored in the first memory component.

Abstract: A semiconductor package comprises a lead frame in the semiconductor package, a chip mounted on the lead frame in the semiconductor package, a sensor in the semiconductor package, a first wire connected to the chip and to the lead frame, and a second wire connected to the sensor and to either the lead frame or the chip. A method comprises providing a lead frame, attaching a chip to the lead frame, wire bonding a first wire to the chip and the lead frame, wire bonding a second wire to either the chip or the lead frame, and depositing a sensor material on the second wire, whereby a sensor is formed.

Abstract: A method comprises shaping a silicon wafer to have a silicon base a silicon mandrel, forming a ceramic interposer over the silicon mandrel, removing the silicon mandrel from the ceramic interposer to form a through opening, and inserting via material in the through opening to form a via in the ceramic interposer. A ceramic interposer has a via extending from the front side to the back side of the ceramic interposer. A semiconductor package has a ceramic interposer made of a SiC powder heated and pressed into an amorphous poly-SiC ceramic with a via extending from the front side to the back side of the interposer, and a semiconductor chip on the front side of the ceramic interposer and connected to the via.

Abstract: Systems and methods track a user's line-of-sight relative to objects through a transparent LCD display to provide information about the objects to be displayed on the display proximate the line-of-sight between the object being viewed and the user's head to create an augmented reality environment for the user. A method comprising: determining a position of an object; determining a position of a transparent display; determining a line-of-sight extending between a user's eye and the object through the transparent display; determining where the line-of-sight intersects the transparent display; and displaying object information corresponding to the object via the transparent display proximate where the line-of-sight intersects the transparent display.

Abstract: A system and method for creating a laser wafer with an array of active regions having different reflectivities created using a focused ion beam tool are disclosed. The semiconductor wafer may include a substrate, a first distributed Bragg reflector (DBR) formed on the substrate, a first active region formed on the first DBR, a second active region formed on the first DBR, a second DBR formed on the first and second active regions, and a contact layer formed on the second DBR. The first active region may include a base material and a first concentration of a doped material introduced by a focused ion beam tool to reflect at a first wavelength. The second active region may include the base material and a second concentration of the doped material introduced by the focused ion beam tool to reflect at a second wavelength.

Abstract: Disclosed herein are apparatus, system, method, and computer-readable medium aspects for a panel-level packaging for integrating photonic and electronic components. A system aspect may include a substrate formed from an Ajinomoto Build-Up Film (ABF) material, a photonic integrated circuit (PIC) and an electrical integrated circuit (EIC) mounted on a panel coupled to the substrate, a window formed in the substrate to allow for the placement of a heat spreader, and the heat spreader positioned within the window to dissipate thermal energy generated by at least one of the PIC and the EIC. The panel-level package may function as a pluggable circuit board for use in an electro-optical system. The heat spreader may be thermally coupled to at least one of the PIC and the EIC to enhance heat dissipation efficiency. The substrate may include a plurality of windows containing respective heat spreaders from a plurality of heat spreaders.

Abstract: A system and method for the addition of heat transfer particles in a vertical cavity surface emitting laser (VCSEL) are disclosed. The method may include adding a plurality of nanoparticles to a passivation material. The plurality of nanoparticles may have a thermal conductivity of less than 2,200 Watts per meter-Kelvin (W/m-K) at zero degrees Kelvin. The method may also include forming a passivation layer between an active region and a contact in a vertical cavity surface emitting laser. The passivation layer may include the passivation material and the plurality of nanoparticles.

Abstract: A system and method for an efficient method for creating a silicon on insulator (SOI) wafer are disclosed. The method may include coating an unpolished single-crystalline silicon wafer with a spin-on-glass to create a spin-on-glass layer. The method may also include growing an etch stop layer on a second single-crystalline silicon wafer. The method may additionally include growing a silicon layer on the etch stop layer. The method may include bonding the silicon layer to the spin-on-glass layer. The method may also include polishing back the second single-crystalline silicon wafer. The method may further include removing the etch stop layer to create a silicon on insulator (SOI) substrate.

Abstract: A method is provided comprising communicating with a semi-autonomous or autonomous robot to coordinate retrieval of a sensor pack from a location proximate the first equipment; retrieving sensor data from the sensor pack; inputting the data from the sensor pack to a machine learning model; decoding a response from the machine learning model to identify a specific intervention; and dispatching the semi-autonomous or autonomous robot to the first equipment to perform an intervention.

Abstract: A method performed by a semi-autonomous or autonomous robot comprising retrieving a sensor pack from a deployment location near a first equipment to be monitored, the sensor pack including a processor, a non-transitory computer readable memory, a battery, a data port, and at least one sensor; deploying the sensor pack to the first equipment; retrieving the sensor pack from the first equipment; charging the battery of the sensor pack; downloading sensor data from the sensor pack; and sending downloaded sensor data from the sensor pack to a processor remote from the deployment location.

Abstract: Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier with one or more cooling fins; placing a filler material between at least two of the one or more cooling fins; providing one or more components on the carrier; and removing the filler material. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side onto which the photonic integrated circuit and/or the electronic integrated circuit are mounted. The carrier is configured with cooling protrusions on a side, opposite to the mounting side.

Abstract: Disclosed is a method of panel level packaging of one or more devices. The method comprises: providing a carrier, forming at least one optical waveguide on the carrier, selectively removing the at least one optical waveguide to obtain one or more opening areas, and mounting one or more components to the carrier within the one or more opening areas. Also disclosed is a panel level packaged device, comprising one or more of a photonic integrated circuit and an electronic integrated circuit; and a carrier, having a mounting side with at least one patterned optical waveguide. The photonic integrated circuit and/or the electronic integrated circuit are mounted into one or more opening areas of the at least one patterned optical waveguide.

Abstract: A system and method for a polymer with a low dielectric constant applied in targeted areas of a semiconductor using additive manufacturing and a second polymer having high thermal conductivity encasing the entire semiconductor are disclosed. The method may include applying, using an additive manufacturing technique, a first polymer to a first area of a semiconductor die. The first polymer may include a first filler having a dielectric constant of 3.3 or less. The method may also include applying a second polymer over the first polymer and encapsulating the semiconductor die. The second polymer may be different from the first polymer.

Abstract: Methods to form a three-dimensional semiconductor package comprising a customized ultra-bandwidth elements (CUBE) die coat shielding particles with an electrically insulating coating, disperse the coated shielding particles in a base material to form a mold structure; and position the mold structure proximate the three-dimensional semiconductor package to shield the package from radiation. Devices comprising: a three-dimensional semiconductor package; and a mold structure proximate the three-dimensional semiconductor package, the mold structure comprising: a base material; and shielding particles comprising an electrically insulating coating, wherein the shielding particles are dispersed in the base material.

Abstract: An apparatus may have a light fixture including a housing and a light element located within the housing. The apparatus may also include a face plate coupled to the light fixture. The apparatus may further include a detector. The detector may be coupled to the housing at a location behind a back surface of the face plate.

Abstract: An integrated circuit (IC) package includes a bare die mounted on a substrate, and a conductive routing region including conductive routing structure and an inductor. The conductive routing structure is conductively connected to the bare die, and includes conductive elements formed in multiple conductive routing layers in the conductive routing region. The inductive device includes a winding formed in at least one conductive routing layer of the multiple conductive routing layers.