Abstract: Disclosed are a spinning dope for an aramid and carbon-nanotube composite fiber and a method of manufacturing an aramid and carbon-nanotube composite fiber using the same.

Abstract: A radio frequency (RF) test device such as a spectrum analyzer may include an RF attenuator to attenuate a received RF signal; a mixer to down-convert the attenuated RF signal; an IF attenuator to attenuate the down-converted signal; an analog-to-digital converter (ADC) to digitize the attenuated, down-converted signal; and a processor, which may select attenuation values for one or more of the RF attenuator and the IF attenuator based on an error magnitude vector (EVM) analysis, an RF signal type, and/or a signal level at an input of the ADC. The processor may use a look-up table for the selection. Initial attenuation values may be selected based on an expected RF signal type, RF signal frequency, and/or RF signal bandwidth. The attenuation values may also be selected in an iterative manner stepping the attenuation values up or down.

Abstract: An apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier having an output coupled to the first inductor, a low-noise amplifier having an input coupled to a first terminal of the third inductor, and a fourth inductor having a first terminal and a second terminal, wherein the second terminal of the fourth inductor is coupled to a second terminal of the third inductor. The apparatus also includes a switch coupled between the first terminal of the third inductor and the first terminal of the fourth inductor.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

Abstract: Methods and apparatuses can implement a phase shifter including at least one phase shift unit. In an example aspect, the phase shift unit has an inductive-capacitive (LC) core that includes an inductor to provide an inductance and a transistor to provide a capacitance using a parasitic capacitance thereof. In some implementations, the LC core includes a first connector node, a second connector node, a transistor, a first inductor, and a second inductor. The transistor is coupled between the first and second connector nodes and is configured to provide a capacitance to the LC core. The first inductor is coupled to the first connector node and is configured to provide a first inductance. The second inductor is coupled to the second connector node and is configured to provide a second inductance. Using a pi-type circuit topology for the LC core can reduce an insertion loss of the phase shift unit.

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.

Abstract: Disclosed herein is a digital attenuator, which can improve the variation in the pass phase of the digital attenuator because the difference between parasitic components caused by the turn-on and turn-off operations of the switching transistors of the digital attenuator causes the difference between the pass phases. The digital attenuator of the present invention includes an attenuation circuit unit configured to cause a variation in a pass phase due to a difference between parasitic components caused by turn-on and turn-off operations of switching transistors, and a phase correction unit connected in parallel with the attenuation circuit unit and provided with a series resistor and a low pass filter. Accordingly, variations in pass phase can be eliminated by connecting a low pass filter, connected to series resistors, in parallel with the series switch of an attenuation circuit unit, thus eliminating the influence of the parasitic components.