Abstract: Disclosed is a pulse radar apparatus including a clock generator generating a transmission clock signal, a reception clock signal, and a sensitivity adjustment interval signal, a transmitter radiating a transmission pulse based on the transmission clock signal, and a receiver receiving a first pulse and a second pulse, which are associated with the transmission pulse, with different sensitivities based on the reception clock signal and the sensitivity adjustment interval signal.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

Abstract: Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns.

Abstract: A method for fabricating a ferroelectric device with improved ferroelectric characteristics and which can provide a reliable contact resistance of a barrier metal layer. The method includes forming an adhesion layer and a barrier metal layer to be electrically connected to the contact plug buried in an insulating layer. The adhesion layer and the barrier layer is then patterned to define an upper surface and a sidewall thereof. An oxidation barrier layer is formed on sidewalls of the patterned layer. An oxide electrode layer and a metal electrode layer are formed thereon for forming a lower electrode. Next, a ferroelectric film and an upper electrode layer are formed thereon. Subsequently, the upper electrode layer, ferroelectric film, platinum and the oxide electrode are patterned to form a ferroelectric capacitor. A diffusion barrier layer is then formed to protect the ferroelectric capacitor.

Abstract: An integrated circuit ferroelectric capacitor is fabricated by forming on an integrated circuit substrate, a lower electrode adjacent the substrate, an upper electrode remote from the substrate and a ferroelectric layer therebetween, and forming a first low temperature oxide layer on the upper electrode, opposite the ferroelectric layer. The low temperature oxide may be annealed in oxygen. A second low temperature oxide layer may be formed on the first low temperature oxide layer, opposite the upper electrode, and the second low temperature oxide layer may be annealed in oxygen. The first and second low temperature oxide layers preferably comprise at least one of Plasma Enhanced Tetraethoxysilane (PE-TEOS), undoped silicon glass (USG) and Electron Cyclotron Resonance oxide (ECR-OX). An electrical contact to the lower electrode may be formed between the steps of forming a first low temperature oxide layer and a second low temperature oxide layer.

Abstract: A method of fabricating A ferroelectric memory cell composed of an MOS transistor and A ferroelectric capacitor formed over A semiconductor substrate, comprises the steps of forming A contact hole through an insulating layer to form A contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor, depositing over the contact hole an oxidizable substance layer to combine with the oxygen generated while forming the ferroelectric layer of the ferroelectric capacitor before forming the contact plug in the contact hole, depositing A conductive oxygen compound layer to separate and pass the oxygen to the upper part of the oxidizable substance layer, and forming the contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor.

Abstract: A method of manufacturing a ferroelectric capacitor includes the steps of forming a lower electrode on a substrate, forming a ferroelectric layer on the lower electrode, forming an upper electrode on the ferroelectric layer, forming a wiring layer on the upper electrode, and applying a voltage to an electrode selected from the upper electrode and the lower electrode, the voltage being greater than the operational voltage of the electrode, to regularly align an electric dipole of the ferroelectric layer.

Abstract: An integrated circuit ferroelectric capacitor is fabricated by forming on an integrated circuit substrate, a lower electrode adjacent the substrate, an upper electrode remote from the substrate and a ferroelectric layer therebetween, and forming a first low temperature oxide layer on the upper electrode, opposite the ferroelectric layer. The low temperature oxide may be annealed in oxygen. A second low temperature oxide layer may be formed on the first low temperature oxide layer, opposite the upper electrode, and the second low temperature oxide layer may be annealed in oxygen. The first and second low temperature oxide layers preferably comprise at least one of Plasma Enhanced Tetraethoxysilane (PE-TEOS), undoped silicon glass (USG) and Electron Cyclotron Resonance oxide (ECR-OX). An electrical contact to the lower electrode may be formed between the steps of forming a first low temperature oxide layer and a second low temperature oxide layer.

Abstract: Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns.

Abstract: Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns.

Abstract: A ferroelectric random access memory device is disclosed, which comprises a bit line, a reference bit line, a memory cell, a sense amplifier, and a voltage-supplying circuit. The reference bit line corresponds to the first bit line and has a reference voltage; the memory cell is coupled to the bit line; the sense amplifier operates to sense a voltage difference between the bit line and the reference bit line; and the voltage-supplying circuit operates to supply the bit line and the reference bit line with the same amount of charge before the sense amplifier is activated. According to the present invention, a voltage induced on a bit line during a sensing operation can be maintained at a high level regardless of the an increase in the degree of integration on the ferroelectric random access memory.

Abstract: A method of fabricating A ferroelectric memory cell composed of an MOS transistor and A ferroelectric capacitor formed over A semiconductor substrate, comprises the steps of forming A contact hole through an insulating layer to form A contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor, depositing over the contact hole an oxidizable substance layer to combine with the oxygen generated while forming the ferroelectric layer of the ferroelectric capacitor before forming the contact plug in the contact hole, depositing A conductive oxygen compound layer to separate and pass the oxygen to the upper part of the oxidizable substance layer, and forming the contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor.

Abstract: Nonvolatile ferroelectric-based integrated circuit memory devices utilize reference cells containing linear storage capacitors to inhibit deterioration in reliability typically associated with ferroelectric capacitors which have undergone excessive polarization cycling. These linear storage capacitors are preferably coupled to respective plate lines so that efficient reading operations may be performed. In particular, a nonvolatile memory device is preferably provided which contains a ferroelectric memory cell having an access transistor and a ferroelectric storage capacitor therein. A reference cell is also provided and this reference cell contains an access transistor and a linear storage capacitor therein. In addition, a sense amplifier is provided which has first and second inputs electrically coupled to the access transistors of the ferroelectric memory cell and the reference cell, respectively.

Abstract: Nonvolatile ferroelectric-based integrated circuit memory devices utilize reference cells containing linear storage capacitors to inhibit deterioration in reliability typically associated with ferroelectric capacitors which have undergone excessive polarization cycling. These linear storage capacitors are preferably coupled to respective plate lines so that efficient reading operations may be performed. In particular, a nonvolatile memory device is preferably provided which contains a ferroelectric memory cell having an access transistor and a ferroelectric storage capacitor therein. A reference cell is also provided and this reference cell contains an access transistor and a linear storage capacitor therein. In addition, a sense amplifier is provided which has first and second inputs electrically coupled to the access transistors of the ferroelectric memory cell and the reference cell, respectively.

Abstract: Ferroelectric memory devices include a semiconductor substrate of first conductivity type having a plurality of well regions of second conductivity type therein, and a ferroelectric memory array arranged as a plurality of rows and columns of ferroelectric memory cells extending opposite the plurality of well regions. Each of the ferroelectric memory cells contains source and drain regions of first conductivity type in a corresponding well region, a floating gate extending opposite the corresponding well region and a control gate capacitively coupled by a ferroelectric material to the floating gate. A plurality of plate lines are also provided. Each of the plurality of plate lines is electrically coupled to control gate electrodes of ferroelectric memory cells in a respective row in the memory array. A plurality of bit lines is also provided. Each of the plurality of bit lines is electrically coupled to source regions of ferroelectric memory cells in a respective column in the memory array.