Abstract: Disclosed is a time-division multi-channel transmission and reception system including a transmitter and a receiver. The transmitter includes a first transmit channel that outputs a first transmit signal based on a first time-division pulse signal, a second transmit channel that outputs a second transmit signal based on a second time-division pulse signal, and a time-division pulse generator that generates the first time-division pulse signal and the second time-division pulse signal based on a clock signal. The first transmit signal and the second transmit signal are separated from each other in time.

Abstract: Disclosed is a radar device capable of operating in a dual mode, which includes a transmitter that includes a first signal generator that generates a Doppler radar signal and a second signal generator that generates a Frequency Modulated Continuous Wave (FMCW) radar signal, a receiver that receives a reflected signal reflected from a target and converts the reflected signal to a digital signal, a signal processing circuit that processes the digital signal differently depending on the dual mode to output an output signal, a signal analysis circuit that analyzes the output signal, and a controller that controls operations of the transmitter, the receiver, the signal processing circuit, and the signal analysis circuit, and the dual mode includes a first mode in which the first signal generator is activated and a second mode in which the second signal generator is activated.

Abstract: Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

Abstract: Provided is a drive amplifier. A drive amplifier may include: a main circuit configured to receive an RF input signal and output a first RF output signal; and a selective bias adjustment circuit comprising a first common gate transistor to which a first common gate bias voltage is applied and a second common gate transistor to which a second common gate bias voltage is applied, and configured to output a second RF output signal using the first common gate transistor and the second common gate transistor.

Abstract: Disclosed is a pulse radar apparatus including a clock generator generating a transmission clock signal, a reception clock signal, and a sensitivity adjustment interval signal, a transmitter radiating a transmission pulse based on the transmission clock signal, and a receiver receiving a first pulse and a second pulse, which are associated with the transmission pulse, with different sensitivities based on the reception clock signal and the sensitivity adjustment interval signal.

Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

Abstract: Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.

Abstract: Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.

Abstract: Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

Abstract: Provided herein are a power system based on a beta source and an operating method thereof. The system includes a power generating section including a plurality of beta source-based generators, a power storage section including a plurality of power storages to store electrical energy which is generated from the generators, a multiplexer configured to select at least some of the storages, an optical power learning section to receive electrical signals provided from the storages, and estimate a state of charge (SOC) of each of the storages, through machine learning, an optimal power selecting section to select a power storage, which provides the optimal power, based on the SOC of each of the storages, an output section including a plurality of output devices to output power provided from the storage selected by the optimal power selecting section, and a de-multiplexer to select at least one output device of the output devices.

Abstract: The inventive concept relates to a body composition analysis system. A body composition analysis system according to an embodiment of the inventive concept includes a sinusoidal signal generator, a synchronous detector, and a bioimpedance analyzer. The sinusoidal signal generator converts a digital sinusoidal signal having a target frequency into an analog sinusoidal signal. The synchronous detector extracts a target frequency component of a bioelectrical signal generated in response to an analog sinusoidal signal based on the digital sinusoidal signal. The bioimpedance analyzer calculates the bioimpedance based on the target frequency component of the bioelectrical signal. According to the inventive concept, it is possible to improve the selectivity for extracting the target frequency component of the bioelectrical signal and to reduce the area and variations of characteristics for the implementation of the integrated circuit.

Abstract: Disclosed are a pulse radar apparatus that detects a position and a motion of a target, and an operating method thereof. The pulse radar apparatus includes a clock signal generator that outputs a transmission clock signal and a reception clock signal, a transmitter that generates a first signal, a receiver that receives an echo signal and the reception clock signal, and generates a second signal, and a signal processor that converts the second signal into a digital signal and analyzes the digital signal. The clock signal generator controls a transmission-to-reception clock delay, and generates a synchronization signal. The signal processor converts the digital signal into a representative value and analyzes the second signal using the representative value. The representative value is one of an accumulated sum of the digital signal in a time duration between synchronization signals and an average value of the digital signal in the time duration between synchronization signals.

Abstract: Provided is a fast Fourier transform device for analyzing specific frequency components of an input signal. The fast Fourier transform device includes an address generator that generates an address, based on a first frequency index corresponding to a first frequency, an FFT coefficient table that outputs a first Fourier transform coefficient corresponding to the generated address among Fourier transform coefficients of the first frequency index, and an operator that calculates a frequency characteristic of an input signal associated with the first frequency, based on the input signal and the first Fourier transform coefficient.

Abstract: Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.

Abstract: Disclosed is a radar device capable of operating in a dual mode, which includes a transmitter that includes a first signal generator that generates a Doppler radar signal and a second signal generator that generates a Frequency Modulated Continuous Wave (FMCW) radar signal, a receiver that receives a reflected signal reflected from a target and converts the reflected signal to a digital signal, a signal processing circuit that processes the digital signal differently depending on the dual mode to output an output signal, a signal analysis circuit that analyzes the output signal, and a controller that controls operations of the transmitter, the receiver, the signal processing circuit, and the signal analysis circuit, and the dual mode includes a first mode in which the first signal generator is activated and a second mode in which the second signal generator is activated.

Abstract: Disclosed is a pulse radar apparatus including a clock generator generating a transmission clock signal, a reception clock signal, and a sensitivity adjustment interval signal, a transmitter radiating a transmission pulse based on the transmission clock signal, and a receiver receiving a first pulse and a second pulse, which are associated with the transmission pulse, with different sensitivities based on the reception clock signal and the sensitivity adjustment interval signal.

Abstract: A radar includes a transmitter that generates a first signal that is a frequency modulated continuous wave (FMCW) signal and radiates the generated first signal to an outside, a receiver that receives a second signal based on the first signal and generates a baseband signal of the second signal, a signal processor that extracts a target frequency signal from the baseband signal, and a signal converter that outputs the target frequency signal that is controlled as a digital signal, and wherein the signal processor includes a high pass filter connected to the receiver, that receives the baseband signal, and attenuates a low frequency signal present in the received baseband signal, based on a first cutoff frequency, an amplifier that amplifies the attenuated baseband signal, and a signal controller that removes a direct current component of the amplified baseband signal, based on a second cutoff frequency.

Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

Abstract: Provided is a drive amplifier. A drive amplifier may include: a main circuit configured to receive an RF input signal and output a first RF output signal; and a selective bias adjustment circuit comprising a first common gate transistor to which a first common gate bias voltage is applied and a second common gate transistor to which a second common gate bias voltage is applied, and configured to output a second RF output signal using the first common gate transistor and the second common gate transistor.

Abstract: Disclosed are a pulse radar apparatus that detects a position and a motion of a target, and an operating method thereof. The pulse radar apparatus includes a clock signal generator that outputs a transmission clock signal and a reception clock signal, a transmitter that generates a first signal, a receiver that receives an echo signal and the reception clock signal, and generates a second signal, and a signal processor that converts the second signal into a digital signal and analyzes the digital signal. The clock signal generator controls a transmission-to-reception clock delay, and generates a synchronization signal. The signal processor converts the digital signal into a representative value and analyzes the second signal using the representative value. The representative value is one of an accumulated sum of the digital signal in a time duration between synchronization signals and an average value of the digital signal in the time duration between synchronization signals.