Patents by Inventor Bone-Fong Wu
Bone-Fong Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11901237Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.Type: GrantFiled: July 25, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun Chang, Bone-Fong Wu, Ming-Chang Wen, Ya-Hsiu Lin
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Publication number: 20230335620Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Patent number: 11682714Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.Type: GrantFiled: March 28, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Publication number: 20230010657Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Publication number: 20220359302Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun CHANG, Bone-Fong WU, Ming-Chang WEN, Ya-Hsiu LIN
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Patent number: 11437278Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.Type: GrantFiled: August 4, 2020Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun Chang, Bone-Fong Wu, Ming-Chang Wen, Ya-Hsiu Lin
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Publication number: 20220223718Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Patent number: 11289584Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.Type: GrantFiled: July 23, 2020Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Publication number: 20210336034Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.Type: ApplicationFiled: July 23, 2020Publication date: October 28, 2021Inventors: Bone-Fong Wu, Chih-Hao Yu, Chia-Pin Lin
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Patent number: 10868003Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.Type: GrantFiled: October 25, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
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Publication number: 20200365465Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun CHANG, Bone-Fong WU, Ming-Chang WEN, Ya-Hsiu LIN
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Patent number: 10741450Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.Type: GrantFiled: February 9, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun Chang, Bone-Fong Wu, Ming-Chang Wen, Ya-Hsiu Lin
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Publication number: 20200058650Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.Type: ApplicationFiled: October 25, 2019Publication date: February 20, 2020Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
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Patent number: 10461078Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.Type: GrantFiled: February 26, 2018Date of Patent: October 29, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
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Publication number: 20190267372Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.Type: ApplicationFiled: February 26, 2018Publication date: August 29, 2019Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
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Publication number: 20190164838Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.Type: ApplicationFiled: February 9, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Yun CHANG, Bone-Fong WU, Ming-Chang WEN, Ya-Hsiu LIN
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Patent number: 8008158Abstract: A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.Type: GrantFiled: July 10, 2008Date of Patent: August 30, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tse-En Chang, Chih-Fu Chang, Bone-Fong Wu, Chieh Chih Ting, Shao Hua Wang, Pu-Fang Chen, Yen Chuang
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Publication number: 20100009506Abstract: A method of forming a dopant implant region in a MOS transistor device having a dopant profile having a target dopant concentration includes implanting a first concentration of dopants into a region of a substrate, where the first concentration of dopants is less than the target dopant concentration, and without annealing the substrate after the implanting step, performing at least one second implanting step to implant at least one second concentration of dopants into the region of the substrate to bring the dopant concentration in the region to the target dopant concentration.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tse-En Chang, Chih-Fu Chang, Bone-Fong Wu, Chieh Chih Ting, Shao Hua Wang, Pu-Fang Chen, Yen Chuang