Abstract: Provided is a method of manufacturing a zinc-plated steel sheet. The method includes: coating a metal on the steel sheet on a steel sheet; annealing the metal coated steel sheet; and zinc plating the annealed steel sheet by dipping in a molten zinc plating bath. Further provided is a method of manufacturing a hot-press part including: coating a metal on the steel sheet on a steel sheet; annealing the metal coated steel sheet; zinc plating the annealed steel sheet by dipping in a molten zinc plating bath; heating the zinc-plated steel sheet; and press forming the heated steel sheet.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include peripheral circuits configured to perform a verify operation on selected memory cells by applying a verify voltage to a word line, and perform a compensation program operation on the selected memory cells by applying a compensation program voltage to the word line; and a control logic configured to control the peripheral circuits such that the compensation program operation is performed by applying the compensation program voltage to the selected memory cells to be programmed to a selected threshold voltage distribution among the threshold voltage distributions other than a highest threshold voltage distribution, wherein the compensation program voltage has a positive voltage lower than the main program voltage most recently applied to the word line.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: A semiconductor device includes: hole source patterns; electron source patterns located between adjacent hole source patterns; a stack structure over the hole source patterns and the electron source patterns; and channel layers penetrating the stack structure, wherein each channel layer is in contact with a corresponding hole source pattern and an electron source pattern adjacent to the corresponding hole source pattern.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

Abstract: Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.

Abstract: A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: A threshold switching device includes a first electrode layer, a second electrode layer, and an insulating layer interposed between the first and second electrode layers and including a plurality of neutral defects. The threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.

Abstract: A method of operating the semiconductor device includes performing an erase operation on a plurality of memory cells, performing a back-tunneling operation by injecting electrons into a storage node from a gate electrode of a memory cell, selected among the plurality of memory cells, and performing a program operation by injecting electrons into the storage node from a channel layer of the selected memory cell.

Abstract: A method of operating the semiconductor device includes performing an erase operation on a plurality of memory cells, performing a back-tunneling operation by injecting electrons into a storage node from a gate electrode of a memory cell, selected among the plurality of memory cells, and performing a program operation by injecting electrons into the storage node from a channel layer of the selected memory cell.

Abstract: An optical fiber unit for air blown installation includes at least one optical fiber having a core layer and a clad layer, a protective layer coated on the surface of the optical fiber; and protrusions made of polymer resin and formed on the outer circumference of the protective layer in a banded shape. The protrusions may be formed either by supplying polymer resin to the outer circumference of the optical fiber with passing the optical fiber through an extrusion dice in which grooves of a predetermined shape are formed on a hollow inner circumference thereof, or by supplying polymer resin to the outer circumference of the optical fiber through nozzles with moving the optical fiber in a longitudinal direction.