Patents by Inventor Bong-Hwa Jeong
Bong-Hwa Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12159681Abstract: A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.Type: GrantFiled: March 1, 2023Date of Patent: December 3, 2024Assignee: SK hynix Inc.Inventors: Sang Ah Hyun, Yong Ho Seo, Woo Sik Jung, Jun Phyo Lee, Bong Hwa Jeong
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Publication number: 20240161851Abstract: A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.Type: ApplicationFiled: March 1, 2023Publication date: May 16, 2024Applicant: SK hynix Inc.Inventors: Sang Ah HYUN, Yong Ho SEO, Woo Sik JUNG, Jun Phyo LEE, Bong Hwa JEONG
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Patent number: 10236767Abstract: A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.Type: GrantFiled: December 13, 2017Date of Patent: March 19, 2019Assignee: SK hynix Inc.Inventors: Jae-Boum Park, Bong-Hwa Jeong, Chang-Hyun Lee
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Publication number: 20180323703Abstract: A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.Type: ApplicationFiled: December 13, 2017Publication date: November 8, 2018Inventors: Jae-Boum PARK, Bong-Hwa JEONG, Chang-Hyun LEE
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Patent number: 9853641Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a pulse generation circuit configured to generate a first pulse and a second pulse in response to an external voltage. The internal voltage generation circuit may include a pulse synthesis circuit configured for synthesizing the first pulse and the second pulse to generate a synthesis pulse.Type: GrantFiled: April 8, 2016Date of Patent: December 26, 2017Assignee: SK hynix Inc.Inventor: Bong Hwa Jeong
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Publication number: 20170117897Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a pulse generation circuit configured to generate a first pulse and a second pulse in response to an external voltage. The internal voltage generation circuit may include a pulse synthesis circuit configured for synthesizing the first pulse and the second pulse to generate a synthesis pulse.Type: ApplicationFiled: April 8, 2016Publication date: April 27, 2017Inventor: Bong Hwa JEONG
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Patent number: 9374092Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.Type: GrantFiled: September 12, 2014Date of Patent: June 21, 2016Assignee: HYNIX SEMICONDUCTOR INC.Inventor: Bong Hwa Jeong
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Publication number: 20150035578Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.Type: ApplicationFiled: September 12, 2014Publication date: February 5, 2015Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Bong Hwa Jeong
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Patent number: 8836410Abstract: An internal voltage compensation circuit is provided which includes a power up signal generator configured to generate a power up signal, a select signal generator configured to compare a level of a first external voltage with a level of a second external voltage to generate first and second select signals, wherein the second select signal is generated in response to the power up signal, and a voltage compensation unit configured to electrically connect an internal voltage to the first external voltage or the second external voltage in response to the first and second select signals.Type: GrantFiled: June 30, 2008Date of Patent: September 16, 2014Assignee: Hynix Semiconductor Inc.Inventor: Bong Hwa Jeong
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Patent number: 8000164Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.Type: GrantFiled: March 15, 2010Date of Patent: August 16, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
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Patent number: 8000163Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.Type: GrantFiled: March 15, 2010Date of Patent: August 16, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
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Patent number: 7957213Abstract: A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the core voltage to the compensation voltage input node; a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal; a power compensating unit configured to selectively supply the external power source voltage to the compensation voltage input node in response to the compensation control signal; and a power supply unit configured to supply a voltage at the compensation voltage input node or the external power source voltage to a sense-amp driver in response to a first power control signal or a second power control signal.Type: GrantFiled: May 21, 2009Date of Patent: June 7, 2011Assignee: Hynix Semiconductor, Inc.Inventor: Bong-Hwa Jeong
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Patent number: 7944275Abstract: Disclosed are a high voltage pumping circuit and a VPP pumping method using the same. The high voltage pumping circuit includes an initializing unit for initializing a high voltage in response to a first enable signal, a first pump for pumping the high voltage in response to the first enable signal, a second pump for pumping the high voltage in response to a second enable signal and a first mode signal, and a mode signal transmitting unit for generating a second mode signal in response to the second enable signal and the first mode signal. The driving of the initializing unit and the first pump is controlled in response to the first pump and the second mode signal.Type: GrantFiled: November 26, 2008Date of Patent: May 17, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae Hoon Kim, Bong Hwa Jeong
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Publication number: 20100188915Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.Type: ApplicationFiled: March 15, 2010Publication date: July 29, 2010Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
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Publication number: 20100188914Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.Type: ApplicationFiled: March 15, 2010Publication date: July 29, 2010Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
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Patent number: 7710809Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.Type: GrantFiled: April 12, 2007Date of Patent: May 4, 2010Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hong Ahn, Bong-Hwa Jeong, Saeng-Hwan Kim, Shin-Ho Chu
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Publication number: 20090237147Abstract: Disclosed are a high voltage pumping circuit and a VPP pumping method using the same. The high voltage pumping circuit includes an initializing unit for initializing a high voltage in response to a first enable signal, a first pump for pumping the high voltage in response to the first enable signal, a second pump for pumping the high voltage in response to a second enable signal and a first mode signal, and a mode signal transmitting unit for generating a second mode signal in response to the second enable signal and the first mode signal. The driving of the initializing unit and the first pump is controlled in response to the first pump and the second mode signal.Type: ApplicationFiled: November 26, 2008Publication date: September 24, 2009Inventors: Jae Hoon Kim, Bong Hwa Jeong
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Publication number: 20090231012Abstract: An external voltage level down circuit includes a first level down unit which receives a first control signal enabled in a power down mode and down-converts a level of a first external voltage, a control signal generating unit which generates a second control signal in response to the down-converted level of the first external voltage, and a second level down unit which receives the second control signal and down-converts a level of a second external voltage.Type: ApplicationFiled: December 31, 2008Publication date: September 17, 2009Inventor: Bong Hwa Jeong
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Publication number: 20090225620Abstract: A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the core voltage to the compensation voltage input node; a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal; a power compensating unit configured to selectively supply the external power source voltage to the compensation voltage input node in response to the compensation control signal; and a power supply unit configured to supply a voltage at the compensation voltage input node or the external power source voltage to a sense-amp driver in response to a first power control signal or a second power control signal.Type: ApplicationFiled: May 21, 2009Publication date: September 10, 2009Applicant: SNK Patent Law OfficesInventor: Bong Hwa JEONG
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Patent number: 7554877Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.Type: GrantFiled: February 26, 2008Date of Patent: June 30, 2009Assignee: Hynix Semiconductor, Inc.Inventors: Tae-Jin Kang, Bong-Hwa Jeong