Patents by Inventor Bong-Hyun Choi
Bong-Hyun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119851Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.Type: ApplicationFiled: September 29, 2023Publication date: April 11, 2024Inventors: Eun Young LEE, Min Jung KIM, Yeun Hee KANG, Bong Hyun CHOI, Tae Un KIM, Soo Hyun LEE, Young Ho KIM, Chan Kyu CHOI, Jin Mo KU, Jong Won KIM
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Patent number: 11791287Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: GrantFiled: August 31, 2021Date of Patent: October 17, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Publication number: 20210398915Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: ApplicationFiled: August 31, 2021Publication date: December 23, 2021Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Patent number: 11133267Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: GrantFiled: December 20, 2018Date of Patent: September 28, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Patent number: 10950704Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.Type: GrantFiled: June 14, 2019Date of Patent: March 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jun Shin, Si-Wan Kim, Bong-Hyun Choi
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Patent number: 10930671Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.Type: GrantFiled: July 17, 2019Date of Patent: February 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jun Shin, Bong-Hyun Choi
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Publication number: 20200203495Abstract: A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.Type: ApplicationFiled: June 14, 2019Publication date: June 25, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Seung-Jun SHIN, Si-Wan Kim, Bong-Hyun Choi
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Patent number: 10685980Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.Type: GrantFiled: February 6, 2019Date of Patent: June 16, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Soo Kim, Si Wan Kim, Jun Hyoung Kim, Kyoung Taek Oh, Bong Hyun Choi
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Publication number: 20200119043Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.Type: ApplicationFiled: July 17, 2019Publication date: April 16, 2020Inventors: SEUNG-JUN SHIN, BONG-HYUN CHOI
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Publication number: 20190393240Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.Type: ApplicationFiled: February 6, 2019Publication date: December 26, 2019Inventors: Kwang Soo KIM, Si Wan Kim, Jun Hyoung Kim, Kyoung Taek Oh, Bong Hyun Choi
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Publication number: 20190333872Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.Type: ApplicationFiled: December 20, 2018Publication date: October 31, 2019Inventors: Geun Won Lim, Seok Cheon Baek, Ji Sung Cheon, Jong Woo Shin, Bong Hyun Choi
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Patent number: 9330931Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.Type: GrantFiled: December 12, 2014Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Min-sung Song, Jin-hyun Shin, Jae-hwang Sim, Joon-sung Lim, Bong-hyun Choi
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Publication number: 20150348795Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.Type: ApplicationFiled: December 12, 2014Publication date: December 3, 2015Inventors: Min-sung Song, Jin-hyun Shin, Jae-hwang Sim, Joon-sung Lim, Bong-hyun Choi
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Patent number: 7112831Abstract: Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.Type: GrantFiled: May 6, 2004Date of Patent: September 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Kim, Jong-Mil Youn, Bong-Hyun Choi
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Publication number: 20040223353Abstract: Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.Type: ApplicationFiled: May 6, 2004Publication date: November 11, 2004Inventors: Jin-Ho Kim, Jong-Mil Youn, Bong-Hyun Choi