Abstract: A nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.

Abstract: A semiconductor device and a fabrication method thereof which are capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming impurity areas around the trenches, include a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of the plurality of trenches, second impurity areas formed on the bottom surfaces of the first impurity areas along the outer surfaces of the trenches, an insulating film filled in the trenches, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trenches, and a gate electrode formed on the gate insulating film.

Abstract: A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate, oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.

Abstract: A method of fabricating a mask ROM includes forming a trench on a first conductivity type semiconductor substrate, implanting a second conductivity type impurity ion in at least a surface portion of the semiconductor substrate where the trench is formed, forming an insulating oxide layer on a surface of the semiconductor substrate, including a surface of the trench, forming gate oxide layers of both sides of the trench, forming first and second gates on the gate oxide layers and forming a first conductivity type channel by implanting a first conductivity type impurity ion in one side of the trench. As such, the resulting mask ROM includes two transistors on either side of a trench having channels along the side walls of the trench. The resulting mask ROM has a reduced surface width, enhancing integration.

Abstract: A semiconductor device and a fabrication method thereof which are capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming impurity areas around the trenches, include a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of the plurality of trenches, second impurity areas formed on the bottom surfaces of the first impurity areas along the outer surfaces of the trenches, an insulating film filled in the trenches, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trenches, and a gate electrode formed on the gate insulating film.

Abstract: A NAND cell memory block array includes word lines and active regions arranged in X and Y directions. When a voltage of Vcc is applied to the word lines arranged in the X direction, a voltage of -Vcc is applied to the word lines arranged in the Y direction to turn off all transistors placed under the word lines arranged in the Y direction, thereby blocking the current path of the transistor. When a voltage of Vcc is applied to the word lines arranged in the Y direction, a voltage of -Vcc is applied to the word lines arranged in the X direction to turn off all transistors placed under the word lines arranged in the X direction, thereby blocking the current path of the transistor. The memory blocks arranged in the X and Y direction interweave or interleave with each other such that integration density can be doubled.