Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A three dimensional image display device includes a display panel and shutter glasses. White image data is displayed during a white image data input period which is disposed before an input period of left eye image data or an input period of right eye image data. As a result, the luminance of a three dimensional image display device may be increased.

Abstract: A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

Abstract: A display device includes a first insulation substrate, a gate line disposed on the first insulation substrate, a semiconductor layer disposed on the gate line, a data line insulated from and crossing the gate line and including a source electrode and a drain electrode facing the source electrode, a first insulating layer disposed on the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a second insulating layer disposed on the pixel electrode, a common electrode disposed on the second insulating layer, and a shielding pattern part disposed on a same layer as the pixel electrode and overlapping the data line.

Abstract: A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.

Abstract: A display panel includes a first substrate, a second substrate which faces the first substrate, is smaller than the first substrate so that an edge of the first substrate is exposed in a plan view, a fixing member disposed on the exposed edge of the first substrate, and a bonding member disposed between the first substrate and the fixing member.

Abstract: A display panel includes a plurality of pixels disposed in an active area and arranged substantially in a matrix form including a pixel row and a pixel column, a first gate line disposed adjacent to a first side n of the pixel row and connected to a first pixel in the pixel row, a second gate line disposed adjacent to a second side of the pixel row and connected to a second pixel in the pixel row, a plurality of data lines crossing the first and second gate lines, where the pixels in a pair of adjacent pixel columns are connected to a same data line, and a blocking pattern which overlaps a pixel column disposed in an end portion of the active area.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a pixel array having a plurality of pixels in a matrix on a substrate. First and second pixels are adjacent to each other along a first direction. The first and second pixels each include first and second switching elements. A first common gate line extends in a second direction different from the first direction and is commonly connected to the first and second switching elements. First and second data lines extend in the first direction and are connected to the first and second switching elements, respectively.

Abstract: A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality.

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract: A gate driving circuit includes a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal. Each stage of the plurality of stages includes; a voltage output part which outputs the gate voltage, an output driving part which drives the voltage output part, a holding part which holds the gate line at an off-voltage, and a discharge part arranged at a first end of the gate line to discharge the gate line to the off-voltage in response to the gate voltage output from the voltage output part.

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

Abstract: A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

Abstract: A touch sensible display device includes a display panel. The display panel includes a plurality of pixels, a plurality of image data lines transferring image data signals to the plurality of pixels and each positioned between two neighboring pixels, a plurality of image scanning lines transferring image scanning signals to the plurality of pixels, a plurality of first sense data lines transferring first sense data signals and each positioned between two neighboring pixels without the image data line interposed therebetween, and a plurality of first sensing units connected with the plurality of first sense data lines and sensing a touch to the display panel.

Abstract: A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.

Abstract: In a liquid crystal display apparatus, a first control signal bus line receives a first control signal. A second control signal bus line receives a second control signal that lags behind the first control signal. A de-multiplexer circuit includes a first switching element and a second switching element. The first switching element switches a current path between a first source line and a first data line in response to the first control signal, and the second switching element switches a current path between the first source line and a second data line in response to the second control signal. A pixel part includes a first pixel connected to the first control signal bus line and corresponding to a first color filter, a second pixel connected to the second control signal bus line and corresponding to a second color filter, and a third pixel corresponding to a third color filter, wherein the third pixels are alternately connected to the first control signal bus line and the second control signal bus line.

Abstract: A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

Abstract: A display substrate includes a first switching element, a second switching element, a first pixel electrode, a second pixel electrode, a main storage electrode and a sub-storage electrode. The first switching element is connected to a data line and a first gate line. The second switching element is connected to the data line and a second gate line adjacent to the first gate line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The main storage electrode is disposed in an area between the first pixel electrode and the second electrode to overlap with first ends of the first and second pixel electrodes. The sub-storage electrode is spaced apart from the first and second gate lines.