Abstract: A winding member, including a winding core for an electrode assembly, winding a positive electrode plate, a negative electrode plate, and a first separator, the winding core including a pair of clamps extending along a longitudinal direction of the winding core a base portion coupled to a first and second end of each of the clamps the clamps being spaced apart from each other vertically around an insertion groove, the clamps including a first clamp and a second clamp extending along the longitudinal direction the first clamp including a pair of protrusions protruding in the direction of the second clamp on an inner surface of the first clamp, and at least one of the pair of protrusions fixing a winding-front end of the first separator inserted into the insertion groove to an inner surface of the second clamp.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

Abstract: A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Abstract: A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.

Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.

Abstract: Methods of fabricating a nonvolatile memory device include forming a trench mask pattern on a semiconductor substrate including a first region and a second region. Substrate trenches defining active regions are formed in the semiconductor substrate in the first region and the second region using the trench mask pattern as a mask. Device isolation layer patterns are formed on the semiconductor substrate including the trench mask pattern and substrate trenches. The device isolation patterns fill the substrate trenches in the first region and in the second region. First and second openings are formed exposing top surfaces of the corresponding active regions in the first and second regions by removing the trench mask pattern. The second opening has a greater width than the first opening. A first lower conductive pattern is formed in the first opening and has a bottom portion in a lower region of the first opening and an extended portion extending from the bottom portion to an upper region of the first opening.

Abstract: Non-volatile memory devices include a substrate with first and second semiconductor active regions therein. These active regions are separated from each other by a trench isolation region, which has a recess therein that extends along its length. First and second floating gate electrodes are provided. These first and second floating gate electrodes extend on the first and second semiconductor active regions, respectively. A control electrode is provided that extends between the first and second floating gate electrodes and into the recess in the trench isolation region. The recess in the trench isolation region is sufficiently deep so that the control electrode, which extends into the recess, operates to reduce (e.g., block) a parasitic coupling capacitance between the first and second floating gate electrodes.