Patents by Inventor Bongjin Jung

Bongjin Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210058334
    Abstract: Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: John GRETH, Arvind SRINIVASAN, David ARDITTI ILITZKY, Robert SOUTHWORTH, Gaspar MORA PORTA, Scott DIESING, Bongjin JUNG, Prasad SHABADI
  • Publication number: 20210058343
    Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.
    Type: Application
    Filed: August 21, 2019
    Publication date: February 25, 2021
    Inventors: John GRETH, Arvind SRINIVASAN, Robert SOUTHWORTH, David ARDITTI ILITZKY, Bongjin JUNG, Gaspar MORA PORTA
  • Publication number: 20200412659
    Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 31, 2020
    Inventors: David ARDITTI ILITZKY, John GRETH, Robert SOUTHWORTH, Karl S. PAPADANTONAKIS, Bongjin JUNG, Arvind SRINIVASAN
  • Publication number: 20200412670
    Abstract: Examples describe an egress subsystem that can be used to schedule fetching and transmission of packets from a switch fabric. Segments of a packet can be requested from a switch fabric and stored in a re-order buffer to re-order any segments that are received out of order from the switch fabric. A header segment re-order buffer can be used to re-order segments of a header. After a header of a packet is available in the header segment re-order buffer, the header can be processed before the entire associated body is received from the switch fabric. A jitter threshold scheme can gate egress of a body from a re-order buffer unless a time threshold or amount threshold is met. The egress subsystem can track a state of packet segments from request to transmission, A flow control message received at the egress subsystem can cause packets in certain states to be paused and not permitted to egress.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 31, 2020
    Inventors: David ARDITTI ILITZKY, Robert SOUTHWORTH, John GRETH, Arvind SRINIVASAN, Travis J. YOUNG, Luis Alfonso MAEDA NUNEZ, James KUNZ, Bongjin JUNG
  • Patent number: 10204049
    Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Vedaraman Geetha, Jeffrey D. Chamberlain, Sailesh Kottapalli, Ganesh Kumar, Henk G. Neefs, Neil J. Achtman, Bongjin Jung
  • Patent number: 10193826
    Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 29, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, Jr., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
  • Publication number: 20180081808
    Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.
    Type: Application
    Filed: January 6, 2012
    Publication date: March 22, 2018
    Applicant: INTEL CORPORATION
    Inventors: Vedaraman GEETHA, Jeffrey D. CHAMBERLAIN, Sailesh KOTTAPALLI, Ganesh KUMAR, Henk G. NEEFS, Neil J. ACHTMAN, Bongjin JUNG
  • Patent number: 9792212
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
  • Publication number: 20170019350
    Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: Bahaa Fahim, Yen-Cheng Liu, Chung-Chi Wang, Donald C. Soltis, JR., Terry C. Huang, Tejpal Singh, Bongjin Jung, Nazar Syed Haider
  • Patent number: 9304922
    Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja
  • Publication number: 20160077970
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga, Eric Delano, Ren Wang
  • Patent number: 9288260
    Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: James R. Vash, Vida Vakilotojar, Bongjin Jung, Yen-Cheng Liu
  • Patent number: 9207753
    Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: James R. Vash, Pritpal S. Ahuja, Bongjin Jung, Jeffrey D. Chamberlain
  • Publication number: 20150160720
    Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.
    Type: Application
    Filed: October 21, 2014
    Publication date: June 11, 2015
    Inventors: James R. Vash, Pritpal S. Ahuja, Bongjin Jung, Jeffrey D. Chamberlain
  • Patent number: 8868951
    Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: October 21, 2014
    Assignee: Intel Corporation
    Inventors: James R. Vash, Pritpal S. Ahuja, Bongjin Jung, Jeffrey D. Chamberlain
  • Publication number: 20140297967
    Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.
    Type: Application
    Filed: June 17, 2014
    Publication date: October 2, 2014
    Inventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja
  • Publication number: 20140214955
    Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.
    Type: Application
    Filed: October 8, 2013
    Publication date: July 31, 2014
    Inventors: James R. Vash, Vida Vakilotojar, Bongjin Jung, Yen-Cheng Liu
  • Patent number: 8769211
    Abstract: Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores. A first and second core interface co-located with the first and second processing cores respectively maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Rishan Tan
  • Patent number: 8756349
    Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 28, 2013
    Date of Patent: June 17, 2014
    Assignee: Intel Corporation
    Inventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja
  • Publication number: 20140115197
    Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2013
    Publication date: April 24, 2014
    Inventors: James R. Vash, Bongjin Jung, Pritpal S. Ahuja