Patents by Inventor Bong Kil Kim
Bong Kil Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7906387Abstract: A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.Type: GrantFiled: November 11, 2008Date of Patent: March 15, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Bong Kil Kim
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Patent number: 7632732Abstract: A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a second mask pattern over the silicon substrate and using the formed second mask pattern to form a first drift region; removing the second mask pattern; forming a third mask pattern and using the formed third mask pattern to form a second drift region; removing the third mask pattern; forming a field oxide film over the silicon substrate; and introducing first conductive impurity ions into an upper surface of the silicon substrate by channel ion implantation.Type: GrantFiled: December 28, 2008Date of Patent: December 15, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Bong-Kil Kim
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Publication number: 20090166719Abstract: Embodiments relate to an LDMOS semiconductor device mask that may reduce current leakage under a gate-off condition. According to embodiments, an LDMOS semiconductor device mask may include a moat mask to define a moat region, an NDT mask to define an N drift region, a PDT mask to define a P drift region, and a gate mask to form a gate. According to embodiments, a PDT mask may be configured to expose a field region of a semiconductor device.Type: ApplicationFiled: December 28, 2008Publication date: July 2, 2009Inventor: Bong-Kil Kim
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Publication number: 20090170257Abstract: A method of manufacturing a transistor may include: forming a first well over a silicon substrate; forming a first mask pattern over the silicon substrate and using the formed first mask pattern to form a second well; removing the first mask pattern; forming a second mask pattern over the silicon substrate and using the formed second mask pattern to form a first drift region; removing the second mask pattern; forming a third mask pattern and using the formed third mask pattern to form a second drift region; removing the third mask pattern; forming a field oxide film over the silicon substrate; and introducing first conductive impurity ions into an upper surface of the silicon substrate by channel ion implantation.Type: ApplicationFiled: December 28, 2008Publication date: July 2, 2009Inventor: Bong-Kil Kim
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Publication number: 20090166737Abstract: A method for manufacturing a transistor is disclosed, which is capable of improving matching characteristics of regions within a transistor or among transistors on a wafer, from wafer-to-wafer, or from lot-to-lot. The method includes forming a photoresist pattern on a semiconductor substrate including an isolation layer, forming a drift region by implanting first and second dopant ions using the photoresist pattern as a mask, forming a gate oxide layer on the semiconductor substrate, forming a poly gate on the gate oxide layer, forming source and drain regions a predetermined distance from the poly gate, and forming a silicide layer on the above structure.Type: ApplicationFiled: November 11, 2008Publication date: July 2, 2009Inventor: Bong Kil KIM
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Publication number: 20090011588Abstract: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.Type: ApplicationFiled: August 29, 2008Publication date: January 8, 2009Inventor: BONG KIL KIM
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Patent number: 7432157Abstract: Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer.Type: GrantFiled: September 24, 2004Date of Patent: October 7, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Bong Kil Kim
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Patent number: 7105887Abstract: Memory cell structures and methods of fabricating the same are disclosed. An illustrated fabrication method comprises: forming spacers to isolate and protect a gate area (including a floating gate and a control gate); forming a gap filling layer over a substrate including the gate area and the spacers; and depositing an insulating layer over the gate area and the gap filling layer. The spacers may be formed of SiN. The gap filling layer may be formed by depositing undoped polysilicon or amorphous silicon over the gate area and the spacers, and by performing an anisotropic etching of the undoped polysilicon or amorphous silicon.Type: GrantFiled: December 29, 2003Date of Patent: September 12, 2006Assignee: Dongbu Electronics, Co., Ltd.Inventors: Hyuk Park, Bong Kil Kim
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Publication number: 20060160253Abstract: A method and apparatus for regulating the temperature a wafer is provided. The apparatus may include a temperature controlling unit provided within the chamber and regulating the temperature of the wafer; a wafer support pin for adjusting the position of the wafer with respect to the temperature controlling unit; and/or a positioning assembly for adjusting the wafer support pin by which the position of the wafer is controlled. The temperature of a wafer baked at a high temperature may be regulated by performing a series of temperature controlling operation in order to reduce the possibility of fracturing the wafer due to a change in temperature.Type: ApplicationFiled: January 17, 2006Publication date: July 20, 2006Inventors: Bong-Kil Kim, Dae-Ho Go, Yun-Jung Moon
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Patent number: 7008856Abstract: A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.Type: GrantFiled: December 31, 2003Date of Patent: March 7, 2006Assignee: DongbuAnam SemiconductorInventors: Chang Hun Han, Bong Kil Kim
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Publication number: 20040157403Abstract: A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.Type: ApplicationFiled: December 31, 2003Publication date: August 12, 2004Inventors: Chang Hun Han, Bong Kil Kim
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Publication number: 20040142530Abstract: Memory cell structures and methods of fabricating the same are disclosed. An illustrated fabrication method comprises: forming spacers to isolate and protect a gate area (including a floating gate and a control gate); forming a gap filling layer over a substrate including the gate area and the spacers; and depositing an insulating layer over the gate area and the gap filling layer. The spacers may be formed of SiN. The gap filling layer may be formed by depositing undoped polysilicon or amorphous silicon over the gate area and the spacers, and by performing an anisotropic etching of the undoped polysilicon or amorphous silicon.Type: ApplicationFiled: December 29, 2003Publication date: July 22, 2004Inventors: Hyuk Park, Bong Kil Kim
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Patent number: 6472752Abstract: A flash memory device is configured to address the problems that charges generated when via hole is etched is charged to a junction region through a metal line and are thus concentrated on a tunnel oxide film, thus making distribution of a threshold voltage over a cell uneven when a device is driven. In order to solve the problems, the device has a junction region in an outside circuit region so charges generated when via hole is etched is concentrated on the junction region formed in the outside circuit region. Thus, it can prevent concentration of the charges on the cell and thus make uniform distribution of the threshold voltage over a cell array.Type: GrantFiled: November 22, 2000Date of Patent: October 29, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Bong Kil Kim, Sung Mun Jung
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Patent number: 6455374Abstract: The present invention relates to a method of manufacturing a flash memory device. According to the present invention, a dielectric film is formed and an amorphous silicon layer is then formed to mitigate a topology generated by patterning of a first polysilicon layer in a cell region. The amorphous silicon layer serves as a protection layer of the dielectric film in the cell region when a gate oxide film in a peripheral circuit region is formed. Therefore, the present invention can not only improve the resistance of a word line in the cell region but also improve the film quality of the dielectric film and the gate oxide film in the peripheral circuit region.Type: GrantFiled: December 27, 2001Date of Patent: September 24, 2002Assignee: Hynix Semiconductor Inc.Inventors: Keun Woo Lee, Bong Kil Kim, Ki Jun Kim, Keon Soo Shim