Abstract: Embodiments of this application relate to the field of semiconductor technologies, and provide composite substrate that comprises: a first silicon carbide layer comprising monocrystalline silicon carbide, and a second silicon carbide layer bonded to the first silicon carbide layer, wherein defect density of at least a part of the second silicon carbide layer is greater than defect density of the first silicon carbide layer.

Abstract: A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.

Abstract: A trench gate semiconductor includes a substrate having a first conductivity type; an epitaxial layer having the first conductivity type, grown on the substrate; a well region having a second conductivity type, formed on a surface layer of the epitaxial layer; a source region having the first conductivity type, formed on a surface layer of the well region; a first trench, running through the well region from a surface of the source region to the epitaxial layer; a gate, formed in the first trench in a manner of being separated by a gate insulator; and an amorphous semiconductor layer, formed in the first trench and wrapping an outer bottom wall of the gate and corners on two sides of the outer bottom wall in a manner of being separated by the gate insulator, where the amorphous semiconductor layer is made of a low dielectric constant material.

Abstract: A semiconductor device includes a drift region, a first electrode structure, and a second electrode structure, and the first electrode structure and the second electrode structure are located on a same side of the drift region. The first electrode structure includes a first insulation layer and a first electrode. The first insulation layer is located on a periphery of the first electrode. The second electrode structure includes a second insulation layer and a second electrode. The second insulation layer is located on a periphery of the second electrode. A buffer structure is disposed between the first electrode and the second electrode, and the buffer structure is configured to increase accumulation of carriers in the drift region when the semiconductor device is turned on. The buffer structure is disposed between the first electrode and the second electrode, so that flow of carriers stored in the drift region is buffered.

Abstract: A chip and an electronic device are disclosed. The chip includes a main functional area, a protection area, and a transition area located between the main functional area and the protection area. The chip includes a field oxide, a metal layer, and a passivation layer that are sequentially stacked on a semiconductor substrate. In the transition area, the field oxide includes a primary field oxide and at least one secondary field oxide that are disposed at intervals, the secondary field oxide is located on a side of the primary field oxide facing the main functional area, the metal layer extends from the main functional area to a side of the primary field oxide facing away from the semiconductor substrate. The passivation layer extends from a side of the metal layer facing away from the semiconductor substrate to a side of the metal layer facing away from the main functional area.

Abstract: The invention disclose a power supply circuit. The power supply circuit includes one or a plurality of first-stage voltage conversion circuits and one or a plurality of second-stage voltage conversion circuits; an input end of the first-stage voltage conversion circuit is coupled to a power supply; the first-stage voltage conversion circuit is configured to convert a first voltage received at the input end into a second voltage, where the second voltage is less than the first voltage; an input end of the second-stage voltage conversion circuit is coupled to an output end of the first-stage voltage conversion circuit; the second-stage voltage conversion circuit is configured to convert the second voltage into a third voltage, and supply the third voltage to a load.

Abstract: A terminal structure of a power device includes a substrate and a plurality of field limiting rings disposed on a first surface of the substrate. The substrate includes a drift layer and a doped layer. The doped layer is formed through diffusion inward from the first surface of the substrate. The doped layer and the drift layer are a first conductivity type, and an impurity concentration of the doped layer is greater than an impurity concentration of the drift layer. The field limiting rings are a second conductivity type. In the terminal structure, lateral diffusion of impurities in the field limiting rings is limited through a design of the doped layer.

Abstract: This application provides a gallium nitride component and a drive circuit thereof. The gallium nitride component includes: a substrate; a gallium nitride (GaN) buffer layer formed on the substrate; an aluminum gallium nitride (AlGaN) barrier layer formed on the GaN buffer layer; and a source, a drain, and a gate formed on the AlGaN barrier layer. The gate includes a P-doped gallium nitride (P—GaN) cap layer formed on the AlGaN barrier layer, and a first gate metal and a second gate metal formed on the P—GaN cap layer. A Schottky contact is formed between the first gate metal and the P—GaN cap layer, and an ohmic contact is formed between the second gate metal and the P—GaN cap layer. In the technical solution provided in this application, the gallium nitride component is a normally-off component, and is conducive to design of a drive circuit.

Abstract: The invention disclose a power supply circuit. The power supply circuit includes one or a plurality of first-stage voltage conversion circuits and one or a plurality of second-stage voltage conversion circuits; an input end of the first-stage voltage conversion circuit is coupled to a power supply; the first-stage voltage conversion circuit is configured to convert a first voltage received at the input end into a second voltage, where the second voltage is less than the first voltage; an input end of the second-stage voltage conversion circuit is coupled to an output end of the first-stage voltage conversion circuit; the second-stage voltage conversion circuit is configured to convert the second voltage into a third voltage, and supply the third voltage to a load.

Abstract: A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.

Abstract: This application provides a hybrid gate field effect transistor, a method for preparing the hybrid gate field effect transistor, and a switch circuit. The hybrid gate field effect transistor includes a channel layer, and a source, a drain, and a gate structure disposed on the channel layer. The gate structure is a hybrid gate structure prepared from two materials. The gate structure includes a first structural layer and a second structural layer. The second structural layer wraps the first structural layer. The first structural layer is an N-type gallium nitride layer or an intrinsic gallium nitride layer; and the second structural layer is a P-type gallium nitride layer. The gate metal layer is disposed on one side of the gate structure facing away from the channel layer, and the gate metal layer is in ohmic contact with the first structural layer.

Abstract: The technology of this disclosure relates to an IGBT chip integrating a temperature sensor, and relates to the field of power device technologies, to improve accuracy of temperature monitoring of the IGBT chip. The IGBT chip integrating the temperature sensor includes a cell region, an emitter pad, a gate pad, a gate finger structure, a temperature sensing module, and a conductive shielding structure. The emitter pad is electrically connected to emitters of a plurality of IGBT cells. The gate finger structure is connected between the gate pad and gates of the plurality of IGBT cells. The temperature sensing module includes a temperature sensor, an anode pad, a cathode pad, and a metal lead. The temperature sensor and at least a part of the metal lead are located in the gate finger structure and are insulated from the gate finger structure.

Abstract: This application provides an insulated gate bipolar transistor, a motor control unit, and a vehicle. The insulated gate bipolar transistor includes three device structure feature layers that are laminated. An IGBT device structure feature layer (10) and an RC-IGBT device structure feature layer (30) are respectively arranged on two sides of an SJ device structure feature layer (20). The RC-IGBT device structure feature layer (30) includes a collector (12) and a drain (13) that are disposed at a same layer. The insulated gate bipolar transistor further includes a first metal electrode (15) laminated with and electrically connected to the collector (12), and a second metal electrode (14) laminated with and electrically connected to the drain (13), and the first metal electrode (15) is electrically isolated from the second metal electrode (14).

Abstract: A method for thinning a wafer is provided which is related to the field of semiconductor technologies, to resolve problems of a low yield, a complex process, and high preparation costs of a SiC power device. The wafer which may alternatively be understood as a composite substrate, includes a first silicon carbide layer, a dielectric layer, and a second silicon carbide layer that are disposed in a stacked manner. The wafer has a first side and a second side that are opposite to each other, and a side that is of the second silicon carbide layer and that is away from the first silicon carbide layer is the first side of the wafer.

Abstract: Embodiments of this application relate to the field of semiconductor technologies, and provide composite substrate that comprises: a first silicon carbide layer comprising monocrystalline silicon carbide, and a second silicon carbide layer bonded to the first silicon carbide layer, wherein defect density of at least a part of the second silicon carbide layer is greater than defect density of the first silicon carbide layer.

Abstract: Embodiments of this application relate to the field of semiconductor technologies, and provide a composite substrate and a preparation method thereof, a semiconductor device, and an electronic device. The composite substrate includes a bearer layer, a silicon carbide layer, and at least one epitaxial layer. The silicon carbide layer is disposed on the bearer layer and bonded to the bearer layer, and a material of the silicon carbide layer includes monocrystal silicon carbide. The at least one epitaxial layer is disposed on a side that is of the silicon carbide layer and that is away from the bearer layer.

Abstract: Embodiments of this application disclose a semiconductor device, a related chip, and a preparation method. The semiconductor device includes an N-type drift layer and an N-type field stop layer adjacent to the N-type drift layer. A density of free electrons at the N-type field stop layer is higher than a density of free electrons at the N-type drift layer. The N-type field stop layer includes first type impurity particles and second type impurity particles doped with the first type impurity particles, and a radius of the second type impurity particles is greater than a radius of the first type impurity particles. In the N-type field stop layer, an injection density of the first type impurity particles in a region adjacent to the N-type drift layer is higher than an injection density of the first type impurity particles in any other region.

Abstract: Embodiments of a degradation phenomenon treatment method based on a photovoltaic module and a related device are disclosed. A high frequency signal is applied to the photovoltaic module when a degradation phenomenon occurs in the photovoltaic module to protect the photovoltaic module and suppress or eliminate the degradation phenomenon. The degradation phenomenon refers to degradation of electricity generation efficiency of the photovoltaic module under effect of an electric potential. Embodiments of the degradation phenomenon treatment method and the device resolve issues associated with a declined electrical energy conversion capability and decreased electricity generation efficiency of a photovoltaic module caused by a surface polarization phenomenon, a potential induced degradation (PID) phenomenon occurring in the photovoltaic module, or both.

Abstract: A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.

Abstract: The technology of this application relates to a silicon carbide substrate, a silicon carbide device, and a substrate thinning method thereof. The method includes: providing a first substrate, where the first substrate is a silicon carbide substrate, and the first substrate has a silicon surface and a carbon surface that are opposite to each other; forming a silicon carbide device on the silicon surface of the first substrate, and forming a protective layer on the silicon carbide device; performing ion implantation on the carbon surface of the first substrate; providing a second substrate; bonding an ion-implanted first substrate to the second substrate; performing high-temperature annealing on the bonded first substrate and the second substrate to combine ions implanted into the first substrate into gas; and performing separation at a position of ion implantation of the first substrate to obtain a thinned first substrate and a separated first substrate.