Abstract: Disclosed herein are a method and apparatus for a video streaming of an extended reality device. According to an embodiment, the method for the video streaming may include a receiving situation information including user location information and pose information at a current point in time from the extended reality device, predicting changes in user location information and pose information at a preset next point in time using pre-learned artificial intelligence receiving, as input, situation information at the current point in time and situation information at a preset previous point in time, rendering an image texture of a video based on the predicted changes in user location information and pose information at the next point in time and transmitting image data with the image texture rendered at the next point in time to the extended reality device, wherein the situation information at the current point in time and the situation information at the present previous point in time configure consecutive frames.

Abstract: Methods and systems for streaming DRM content are disclosed, and specific embodiments of the present disclosure can prevent communication degradation between a DRM server and a client terminal by reconstructing three-dimensional AR objects of DRM content packaged with an encryption key into a predetermined number of resolutions and then streaming them in segments, decrypting the three-dimensional AR objects of each received resolution matching a client authentication authority, and rendering them over a rendered low-resolution single image.

Abstract: Disclosed herein are a method and apparatus for point cloud video streaming. According to an embodiment, the method for point cloud video streaming may include receiving pose information from a user terminal changing the pose of a virtual camera in a virtual space where a point cloud video is played, by applying the pose information to the virtual camera, rendering an image texture of the point cloud video corresponding to a viewpoint of the virtual camera with the changed pose and transmitting video data with the rendered image texture to the user terminal.

Abstract: Disclosed herein are a method and apparatus for a camera calibration. According to an embodiment, the method for the camera calibration may include a recognition unit configured to recognize a captured calibration pattern, a selection unit configured to select, among a plurality of preset calibration algorithms, a calibration algorithm corresponding to the recognized calibration pattern and an execution unit configurated to perform camera calibration by using the selected calibration algorithm and the captured calibration pattern.

Abstract: A three-dimensional memory device includes a base dielectric layer disposed on a substrate, a stack structure that includes word lines and interlayer dielectric layers that are alternately stacked on the base dielectric layer, a bit line that penetrates the stack structure and extends in a vertical direction perpendicular to a top surface of the substrate, and buried storage patterns interposed between the bit line and the word lines and spaced apart from each other in the vertical direction. Each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate. The widths of the buried storage patterns increase with increasing vertical distance from the substrate.

Abstract: A nonvolatile memory device may include a substrate, a plurality of gate electrodes stacked on the substrate, a first conductive pillar that extends in a first direction and intersects the gate electrodes, a second conductive pillar that extends in the first direction and intersects the gate electrodes, the second conductive pillar being spaced apart from the first conductive pillar, an information storage film between the first conductive pillar and each of the gate electrodes and between the second conductive pillar and each of the gate electrodes, the information storage film including chalcogenide, a conductive layer spaced apart from the gate electrodes in the first direction, a first charge dissipation layer between the first conductive pillar and the conductive layer, and a second charge dissipation layer between the second conductive pillar and the conductive layer, the second charge dissipation layer being spaced apart from the first charge dissipation layer.

Abstract: A low-latency 360 virtual reality (VR) streaming method for estimating a region of interest (ROI) of a user is proposed. The method may include receiving device pose information from a user device, extracting an ROI of a user, based on the device pose information, and generating ROI tile information corresponding to the ROT. The method may also include generating ROI estimation tile information corresponding to a position at which the ROI is to be changed, and requesting, from a streaming server, a tile corresponding to the ROI tile information and the ROI estimation tile information to receive a high-quality tile stream and a low-quality tile stream of full video that includes a low-quality full video tile stream. The method may further include decoding and rendering the high-quality tile stream and the low-quality full video tile stream and providing the rendered video to the user device.

Abstract: An augmented reality (AR) streaming device interoperating with an edge server is proposed. The AR streaming device may include a sensing module including a camera and a certain inertia sensor, a display module streaming AR video, a communication module transmitting or receiving data to or from the edge server and the sensing module. The device may also include a memory and a processor executing a program stored in the memory. When image data and inertia data are obtained through the sensing module, the processor may perform synchronization and encoding on the image data and the inertia data to transmit to the edge server through the communication module. When segmentation rendering-processed AR video is received from the edge server, the processor may perform decoding and blending on the segmentation rendering AR video to perform control to be streamed through the display module.

Abstract: A system and a method for split-rendering for persons with color weakness are proposed. The split-rendering method may include, by a service server, in response to a login of a user device, loading a color weakness profile corresponding to a user of the logging-in user device. The method may also include, by the service server, in response to the user being color-weak in accordance with the loaded color weakness profile, selecting one of a plurality of split-rendering servers. The method may further include, by the service server, transmitting a video content along with the color weakness profile to the selected split-rendering server, and by the service server, transmitting access information about the selected split-rendering server to the user device.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

Abstract: A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Abstract: An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

Abstract: Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns.

Abstract: A method for fabricating a ferroelectric device with improved ferroelectric characteristics and which can provide a reliable contact resistance of a barrier metal layer. The method includes forming an adhesion layer and a barrier metal layer to be electrically connected to the contact plug buried in an insulating layer. The adhesion layer and the barrier layer is then patterned to define an upper surface and a sidewall thereof. An oxidation barrier layer is formed on sidewalls of the patterned layer. An oxide electrode layer and a metal electrode layer are formed thereon for forming a lower electrode. Next, a ferroelectric film and an upper electrode layer are formed thereon. Subsequently, the upper electrode layer, ferroelectric film, platinum and the oxide electrode are patterned to form a ferroelectric capacitor. A diffusion barrier layer is then formed to protect the ferroelectric capacitor.

Abstract: An integrated circuit ferroelectric capacitor is fabricated by forming on an integrated circuit substrate, a lower electrode adjacent the substrate, an upper electrode remote from the substrate and a ferroelectric layer therebetween, and forming a first low temperature oxide layer on the upper electrode, opposite the ferroelectric layer. The low temperature oxide may be annealed in oxygen. A second low temperature oxide layer may be formed on the first low temperature oxide layer, opposite the upper electrode, and the second low temperature oxide layer may be annealed in oxygen. The first and second low temperature oxide layers preferably comprise at least one of Plasma Enhanced Tetraethoxysilane (PE-TEOS), undoped silicon glass (USG) and Electron Cyclotron Resonance oxide (ECR-OX). An electrical contact to the lower electrode may be formed between the steps of forming a first low temperature oxide layer and a second low temperature oxide layer.

Abstract: A method of fabricating A ferroelectric memory cell composed of an MOS transistor and A ferroelectric capacitor formed over A semiconductor substrate, comprises the steps of forming A contact hole through an insulating layer to form A contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor, depositing over the contact hole an oxidizable substance layer to combine with the oxygen generated while forming the ferroelectric layer of the ferroelectric capacitor before forming the contact plug in the contact hole, depositing A conductive oxygen compound layer to separate and pass the oxygen to the upper part of the oxidizable substance layer, and forming the contact plug to electrically connect the source region of the MOS transistor and the lower electrode of the ferroelectric capacitor.

Abstract: A method of manufacturing a ferroelectric capacitor includes the steps of forming a lower electrode on a substrate, forming a ferroelectric layer on the lower electrode, forming an upper electrode on the ferroelectric layer, forming a wiring layer on the upper electrode, and applying a voltage to an electrode selected from the upper electrode and the lower electrode, the voltage being greater than the operational voltage of the electrode, to regularly align an electric dipole of the ferroelectric layer.