Abstract: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Abstract: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Abstract: A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor.

Abstract: A method for checking for reliability problems of an integrated circuit that includes determining a total MOS transistor gate area for an entire integrated circuit. Based on the total MOS transistor gate area, a time dependent dielectric breakdown lifetime (TDDB) is calculated.

Abstract: A method of determining a saturation current degradation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation with gate voltage (Vgs) at a level that causes Idsat degradation by bias temperature instability (BTI). A second dependence of the saturation current (Idsat) recovery versus gate voltage (Vgs) is also measured for the MOS integrated circuit fabrication process. A recovery voltage threshold value is determined. The recovery voltage threshold value is indicative of Vgs voltages below which BTI recovery occurs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, a BTI recovery factor is calculated based on an amount of time the Vgs of the first MOS transistor is below the recovery voltage threshold value.

Abstract: A method for checking for reliability problems includes measuring, for a MOS integrated circuit fabrication process, a dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). The saturation current (Idsat) degradation versus drain voltage (Vds) is also measured for the MOS integrated circuit process. The measured data points of an amount of time until a threshold degradation occurs versus Vgs divided by Vds is fitted to a curve in order to determine a first expected lifetime equation that is based on Vgs. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of this simulation, and the first expected lifetime equation, a first expected lifetime for the first MOS transistor is calculated. If the first expected lifetime is less than a lifetime limit, a warning message is generated.

Abstract: A method for checking for reliability problems includes simulating a circuit having at least one MOS transistor that includes a first MOS transistor. Based on the results of this simulation of the circuit, a gate-to-bulk voltage (Vgb) for the first MOS transistor is calculated. A voltage limit based on the length of the channel of the first MOS transistor is selected. If Vgb is greater than the voltage limit, a warning message is generated.

Abstract: A method for checking for reliability problems that includes simulating a circuit having at least one MOS transistor. The circuit includes at least a first MOS transistor. Based on the results of the simulation of the circuit, a bulk-to-source voltage (Vbs) is calculated for the first MOS transistor. Based on the calculated Vbs for the first MOS transistor, a threshold voltage (Vth) for the first MOS transistor is calculated. Based on the Vth, an effective Vgs for the first MOS transistor is calculated. And, based on the effective Vgs, a reliability indicator associated with the first MOS transistor is calculated.

Abstract: A method of adjusting an expected lifetime equation that includes measuring, for a MOS integrated circuit fabrication process, a first dependence of a saturation current (Idsat) degradation versus gate voltage (Vgs). This first dependence is indicative of Idsat degradation at least partially caused by hot carrier injection (HCI). A second dependence of the saturation current (Idsat) degradation versus gate voltage (Vgs) is also measured. This second dependence is indicative of Idsat degradation caused by bias temperature instability (BTI). An artificial HCI lifetime equation is determined. This artificial HCI lifetime equation is based on the second dependence subtracted from the first dependence. A circuit having at least one MOS transistor that includes a first MOS transistor is simulated. Based on the results of the simulation, and the artificial HCI lifetime equation, an Idsat degradation for the first MOS transistor is calculated.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.

Abstract: Reliability testing circuitry is built into the wafer or IC package in the form of one or more individual testers that use small-area transistors as DUTs. Stress can be applied to the DUTs in parallel and information about breakdown, wearout or failure can be obtained from the individual testers. Only a few pads are needed to test hundreds and even thousands of the DUTs of the individual testers. Testing of many DUTs may be performed using a simple power supply and a few probes.

Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.