Abstract: A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a ½ multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Abstract: An input buffer is provided that converts a TTL logic signal to a CMOS logic signal and controls an CMOS output level while eliminating static current consumption even when an external bias voltage is changed. The input buffer improves a low-to-high input signal switching speed. Further, the input buffer can be used for low current and high-speed operation. The input buffer includes an inverter unit having pull-up and pull-down transistors with commonly coupled drains coupled between a power supply voltage and a ground voltage. The input buffer further can include a transistor control unit that receives an output signal of the input buffer to completely turn off the pull-up transistor when the TTL input signal is a high level and rapidly turn on the transistor when the TTL input signal is a low level.

Abstract: The present invention is directed to a digital delay-locked loop for digitally controlling a clock signal delay time and saving synchronization information in a register. After intercepting an input clock signal, the digital delay-locked loop utilizes the saved synchronization information in returning to the normal operation, and furthermore, detects a shifted delay by using a trigger pulse generator in order to reduce power consumption during the rapid synchronization of an internal clock signal to an external clock signal, saves a delay state corresponding to a maximum value of half the period of the external clock signal to a lock target rising edge of the internal clock signal, and thus synchronization time and operating time of the digital delay-loop are reduced, which results in reduced operation power for the predetermined time.

Abstract: Semiconductor memory device which can support a DDR SDRAM latency mode like 2.