Abstract: A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a counter circuit for counting a clock signal in response to a reset signal and decoding the counted clock signal to produce at least one decoding signal; and a fuse circuit comprising a plurality of fuse arrays, each fuse of the plurality of fuse arrays representing chip identification information, for outputting an output signal indicating whether each fuse of the plurality of fuse arrays is cut in response to the at least one decoding signal. The apparatus for recognizing chip identification minimizes the number of pads required for a semiconductor chip, occupies a small portion of a semiconductor device, and reads chip information in a package state of a semiconductor device.