Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

Abstract: We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.

Abstract: A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

Abstract: A technique comprising: determining a correction to a drive voltage for the front plane common electrode of a first display device according to the result of one or more measurements of an optical property for the first display device and the result of one or more measurements of said optical property for one or more other devices including an optical medium having the same optical response as the first display device.

Abstract: We describe a method of reducing artefacts in an image displayed by an active matrix electro-optic display and display driver, the electro-optic display driver comprising a plurality of active matrix pixel drivers each driving a respective pixel of the electro-optic display, each active matrix pixel driver having an associated storage capacitor coupled to a common backplane connection of the display driver, pixels of the electro-optic display having a common pixel electrode, the method comprising: driving the electro-optic display with a null frame during a power-down procedure of the display.

Abstract: A technique comprising: forming laterally-extending switching circuitry of a device for controlling an overlying laterally-extending array of pixel conductors of said device; forming an electrically conductive laterally-extending patterned screen over said switching circuitry via a first insulating region, said patterned screen defining holes for receiving conductive interlayer connects between said switching circuitry and said array of pixel conductors; and thereafter: forming a second insulating region over said patterned screen, forming said array of pixel conductors over said patterned screen via said second insulating region for capacitative coupling with said patterned screen, forming through holes through at least said first and second insulating regions at the locations of said holes defined in said patterned screen, and forming said interlayer connects in said through holes; and wherein said patterned screen is configured such that the area of overlap between the array of pixel conductors and underly

Abstract: A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device.

Abstract: A technique comprising: determining a correction to a drive voltage for the front plane common electrode of a first display device according to the result of one or more measurements of an optical property for the first display device and the result of one or more measurements of said optical property for one or more other devices including an optical medium having the same optical response as the first display device.

Abstract: A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device. Such a configuration allows for improved device performance, resulting from features such as a greater storage capacitance.