Abstract: A method for synthesizing a register transfer level (RTL) based design employs a bottom-up approach to generate a final top-level design. The top-level design is divided into a plurality of sub-modules. Each of the sub-modules is then independently synthesized using an RTL based design approach and independently adapted to conform to timing requirements produced for each of the sub-modules using time budgets that are based on the top-level timing requirements. Once the sub-modules are synthesized and pass individual timing requirements specific for those sub-modules, the sub-modules are integrated to form a top-level design. The top-level design may then be verified for timing requirements and other formal requirements.

Abstract: A method and apparatus for automatically verifying whether a network interface is transmitting frame data properly. Frame data stored in host memory is transmitted to the network interface and to a transmit data checker. The network interface receives, processes and transmits the frame data. The processed frame data is transmitted to a network media and to the transmit data checker. The transmit data checker compares the frame data from the host memory with the processed frame data from the network interface and generates an indicator signal. The indicator signal indicates whether the network interface is transmitting processed frame data properly. The indicator signal is sent to a display which displays the result. The transmit data checker includes a timer for determining the processing time of the network interface. The timer measures the time between reception of the frame data from the host memory and the reception of the transmitted data.

Abstract: A method and apparatus for automatically verifying whether a network interface is receiving frame data properly. A network interface and a received data checker receive frame data from a network media such as a network or a network model. The network interface processes and transmits the frame data to host memory for storage. The host memory stores the frame data and transmits the frame data to the receive data checker. The receive frame checker compares the frame data from the host memory with the frame data from the network media and generates an indicator signal. The indicator signal indicates whether the network interface is receiving frame data properly. The indicator signal is sent to a display which displays the result.

Abstract: An arrangement and method of performing a memory built-in self test (MBIST) on a memory loops together the registers that store the MBIST results. When an error is detected during the MBIST by an MBIST controller, the MBIST results are shifted serially through the register loop as well as off the chip performing the MBIST. Once all the MBIST results are shifted out for further analysis by a host computer, for example, the MBIST controller is in its original state at the time the error was detected as the MBIST results are back in the registers they occupied prior to the shifting out of the MBIST results off the chip.