Abstract: Integrated circuits with clock distribution circuitry are provided. The clock distribution circuitry may include a clock source, a clock distribution network, a frequency encoder placed at the output of the clock source, and one or more frequency decoders placed at the destinations of the clock distribution network. The frequency encoder can be used to obtain calibrated delay settings proportional to a reference clock generated by the clock source. Each frequency decoder can be placed in a closed loop configuration and can use the calibrated delay settings to locally self-generate a recovered clock at the destination during a locked state. During the locked state, clock buffers in the clock distribution network can be powered down to save power.