Abstract: In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.

Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Abstract: A test vehicle, along with methods for fabricating and using a test vehicle, are disclosed herein. In one example, a test vehicle is provided that includes a substrate, at least a first passive die mounted on the substrate, and at least a first test die mounted on the substrate. The first test die includes test circuitry configured to test continuity through solder interconnects formed between the substrate and the first passive die.

Abstract: A thermal management system includes an integrated circuit (IC). The IC includes a plurality of digitally addressable sectors. Each sector includes an on-die sensing element. The on-die sensing element includes an on-die temperature sensor configured to measure a sector temperature and provide an analog signal associated with the sector temperature; and an on-die digitizer configured to generate a digital sensed temperature signal based on the analog signal. The IC further includes a first output configured to output a plurality of digital sensed temperature signals from the plurality of sectors.

Abstract: The disclosure provides simple, low-cost but accurate systems and related methods for on-die temperature sensing typically using calibration and without the need for precision voltage references. In some implementations, the system utilizes two user selectable temperature sensing elements and two user selectable DACs to provide a digital code for the sensed temperature. In some implementations, the two sensing elements can be used to calibrate against each other. For example, calibration can be useful to account for silicon local/global variation. Typically, one of the temperature sensors is diode-based, while the other is resistor-based. However, those of skill in the art will recognize that, in accordance with the disclosure, more than two sensors can be provided that can be calibrated against one another.

Abstract: A circuit for testing bond connections between a first die and a second die is described. The circuit comprises a defect monitoring circuit implemented on the first die, which is configured as a test die; and a plurality of bond connections between the first die and the second die; wherein the defect monitoring circuit is configured to detect a defect in a bond connection of the plurality of bond connections between the first die and the second die. A method of testing bond connections between a first die and a second die is also described.

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) can include a first node comprising a region of a metal layer of an IC manufacturing process and a second node comprising a region of a conductive layer residing on a layer of the IC manufacturing process below the metal layer of the first node. The fuse structure can include a fuse link comprising a conductive material, positioned substantially perpendicular to each of the metal and conductive layers. An upper end of the fuse link couples to the first node and a lower end of the fuse link, that is distal to the upper end, couples to the second node.

Abstract: A fuse structure for a semiconductor integrated circuit (IC) includes an anode comprising conductive material overlaying a diffusion material disposed within a substrate layer of the IC, wherein the diffusion material is electrically isolated from the substrate layer by at least one p-n junction. The fuse structure can include a cathode comprising conductive material overlaying the diffusion material. The fuse structure further can include a fuse link comprising conductive material overlaying the diffusion material, wherein a first end of the fuse link couples to the anode and a second end of the fuse link, that is distal to the first end, couples to the cathode.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: Aspects for locating chip-level defects through emission imaging of a semiconductor device are described. The aspects include providing a semiconductor device for inspection within an emission imaging system. Emission detection from a frontside and backside of the semiconductor device substantially simultaneously is then performed in the emission imaging system, wherein the emissions detected indicate potential defects within the semiconductor device.

Abstract: A method and apparatus for identifying individual semiconductor die that originate from a semiconductor substrate containing a plurality of die is disclosed. Aspects of the invention include physically associating a respective die ID with at least a portion of individual die on the wafer, and storing the die ID and wafer fabrication information in a database. During subsequent testing of the die, the die ID is used to retrieve the wafer fabrication information from the database, thereby aiding a determination as to a cause of a failure of the die.

Abstract: Aspects for revealing active regions of a silicon-on-insulator (SOI) circuit for inspection from a backside of a DUT are described. The aspects include etching a substrate layer of an SOI circuit and removing a buried oxide layer beneath the substrate layer. From these steps, active regions beneath the buried oxide layer are revealed.