Patents by Inventor Boon Yeap
Boon Yeap has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12086049Abstract: Techniques for capacity management in computing systems are disclosed herein. In one embodiment, a method includes analyzing data representing a number of enabled users or a number of provisioned users to determine whether the analyzed data represents an anomaly based on historical data. The method can also include upon determining that the data represents an anomaly, determining a conversion rate between a change in the number of enabled users or the number of provisioned users and a change in a number of active users of the computing service and deriving a future value of the number of active users of the computing service based on both the detected anomaly and the determined conversion rate. The method can further include allocating and provisioning an amount of the computing resource in the distributed computing system in accordance with the determined future value of the active users of the computing resource.Type: GrantFiled: December 30, 2021Date of Patent: September 10, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Jieqiu Chen, Yow-Gwo Wang, Qizhi Xu, Feiyue Jiang, Harsh Mahendra Mehta, Boon Yeap, Dimple Kaul
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Publication number: 20240297972Abstract: An augmented reality apparatus includes a plurality of transmission lines, plural signal-generating circuits, at least one additional transmission line, at least one signal-processing circuit, a multiplexer having a plurality of inputs and at least one output, a plurality of matching networks, and an additional matching network coupling the additional transmission line to the output of the multiplexer. Example AR/VR devices include a camera configured to receive light from the external environment of the device and to provide a camera signal. The camera may include a surface variable lens including a support layer, an optical layer, a membrane layer, and an actuator. A computer-implemented method for anatomical electromyography test design includes identifying a wearable device having a frame including a plurality of electrodes, and calibrating the plurality of electrodes.Type: ApplicationFiled: November 21, 2023Publication date: September 5, 2024Inventors: Hanqiao Zhang, Patrick Codd, Dongmin Yang, Yi Zhou, Yizhi Xiong, Fei Liu, Abhishek Dhanda, Michael Okincha, Linsen Bie, Honghong Peng, Zhaochun Yu, Lidu Huang, Shaomin Xiong, Gabriel Molina, Pablo Castillo Canales, Peng Chen, Danni Luo, Eddie Alex Azuma, Kong Boon Yeap, Dana Jensen, Cameron O'Neill, Guangwu Duan, Raffael Engleitner, David Xu, Yibo Liu, Ankur Verma, Lei Zhao, Yuecheng Li, Dawei Wang
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Publication number: 20230214308Abstract: Techniques for capacity management in computing systems are disclosed herein. In one embodiment, a method includes analyzing data representing a number of enabled users or a number of provisioned users to determine whether the analyzed data represents an anomaly based on historical data. The method can also include upon determining that the data represents an anomaly, determining a conversion rate between a change in the number of enabled users or the number of provisioned users and a change in a number of active users of the computing service and deriving a future value of the number of active users of the computing service based on both the detected anomaly and the determined conversion rate. The method can further include allocating and provisioning an amount of the computing resource in the distributed computing system in accordance with the determined future value of the active users of the computing resource.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Inventors: Jieqiu Chen, Yow-Gwo Wang, Qizhi Xu, Feiyue Jiang, Harsh Mahendra Mehta, Boon Yeap, Dimple Kaul
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Patent number: 10523206Abstract: One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.Type: GrantFiled: March 15, 2018Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Kong Boon Yeap, Yang Liu, Tian Shen, Anjum Mehta
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Patent number: 10475677Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.Type: GrantFiled: August 22, 2017Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Tian Shen, Anil Kumar, Yuncheng Song, Kong Boon Yeap, Ronald G. Filippi, Jr., Linjun Cao, Seungman Choi, Cathryn J. Christiansen, Patrick R. Justison
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Publication number: 20190288690Abstract: One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.Type: ApplicationFiled: March 15, 2018Publication date: September 19, 2019Inventors: Kong Boon Yeap, Yang Liu, Tian Shen, Anjum Mehta
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Publication number: 20190067056Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Tian Shen, Anil Kumar, Yuncheng Song, Kong Boon Yeap, Ronald G. Filippi, JR., Linjun Cao, Seungman Choi, Cathryn J. Christiansen, Patrick R. Justison
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Publication number: 20190066812Abstract: An e-fuse structure including a circuit having an e-fuse operably coupling the circuit to a power source, and a redundant circuit for operably coupling the power source in response to opening of the e-fuse, wherein the e-fuse opens in response to a time-dependent dielectric breakdown (TDDB) percolation current in proximity to the circuit migrating through the e-fuse. A method of programming such an e-fuse structure is also disclosed.Type: ApplicationFiled: August 24, 2017Publication date: February 28, 2019Inventors: Kong Boon Yeap, Tian Shen, Ronald Gene Filippi, JR., Seungman Choi, Linjun Cao
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Patent number: 10151645Abstract: The invention relates to an arrangement and to a method for the synchronous determination of the shear modulus and of the Poisson's number on samples of elastically isotropic and anisotropic materials. In the arrangement, an indenter is movable in parallel with its longitudinal axis (A) in the direction of the surface of a sample such that a force action is exerted on the material by its tip. The force can be determined by a device for measuring this force and the indenter is additionally deflected in translation along at least one further axis. The longitudinal axis (A) of the indenter is aligned at an angle ?90° with respect to the surface of the sample and the indenter carries out an upward movement and a downward movement.Type: GrantFiled: September 2, 2014Date of Patent: December 11, 2018Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Kong Boon Yeap, Malgorzata Kopycinska-Mueller, Ehrenfried Zschech, Martin Gall
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Patent number: 10147783Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.Type: GrantFiled: March 20, 2017Date of Patent: December 4, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Atsushi Ogino, Vikrant Chauhan, Kong Boon Yeap, Ahmed Hassan
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Publication number: 20180269275Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.Type: ApplicationFiled: March 20, 2017Publication date: September 20, 2018Inventors: Atsushi Ogino, Vikrant Chauhan, Kong Boon Yeap, Ahmed Hassan
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Patent number: 9411341Abstract: A vacuum pump controller and a method of making a devise using the same are presented. The vacuum pump controller comprises detectors for detecting whether a cassette is present in a semiconductor processing load lock; and controllers for sending control signals to a vacuum pump to control the speed voltage of the vacuum pump. The vacuum pump controller may further send control signals to control the supply of N2/H2 gas, cooling water and other vacuum pump accessories.Type: GrantFiled: May 23, 2013Date of Patent: August 9, 2016Inventors: Chin Fong Lee, Ming Zhu, Chuin Boon Yeap
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Publication number: 20150066394Abstract: The invention relates to an arrangement and to a method for the synchronous determination of the shear modulus and of the Poisson's number on samples of elastically isotropic and anisotropic materials. In the arrangement, an indenter is movable in parallel with its longitudinal axis (A) in the direction of the surface of a sample such that a force action is exerted on the material by its tip. The force can be determined by a device for measuring this force and the indenter is additionally deflected in translation along at least one further axis. The longitudinal axis (A) of the indenter is aligned at an angle ?90° with respect to the surface of the sample and the indenter carries out an upward movement and a downward movement.Type: ApplicationFiled: September 2, 2014Publication date: March 5, 2015Inventors: Kong Boon YEAP, Malgorzata KOPYCINSKA-MUELLER, Ehrenfried ZSCHECH, Martin GALL
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Patent number: 8685861Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.Type: GrantFiled: August 2, 2006Date of Patent: April 1, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Chih Ping Yong, Peter Chew, Chuin Boon Yeap, Hoon Lian Yap, Ranbir Singh, Nace Rossi, Jovin Lim
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Publication number: 20130317640Abstract: A vacuum pump controller and a method of making a devise using the same are presented. The vacuum pump controller comprises detectors for detecting whether a cassette is present in a semiconductor processing load lock; and controllers for sending control signals to a vacuum pump to control the speed voltage of the vacuum pump. The vacuum pump controller may further send control signals to control the supply of N2/H2 gas, cooling water and other vacuum pump accessories.Type: ApplicationFiled: May 23, 2013Publication date: November 28, 2013Inventors: Chin Fong LEE, Ming ZHU, Chuin Boon YEAP
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Publication number: 20080029853Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.Type: ApplicationFiled: August 2, 2006Publication date: February 7, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chih Ping Yong, Peter Chew, Chuin Boon Yeap, Hoon Lian Yap, Ranbir Singh, Nace Rossi, Jovin Lim
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Patent number: 7297640Abstract: A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.Type: GrantFiled: January 13, 2005Date of Patent: November 20, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Jun Xie, Hoon Lian Yap, Chuin Boon Yeap, Weoi San Lok
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Publication number: 20070217169Abstract: A clamshell housing is used in a stand-alone configuration of “DualPlay” instrument modules. The housing comprises first and second sections pivotally connected by a hinge mechanism at a hinge end of the clamshell housing that allows rotation of the first and second sections relative to one other between an open and closed position. An open end of the clamshell housing is opposite to the hinge end. A sliding-fastener bumper section slides over the open end and secures the sections in the closed position. A main storage compartment is formed by the first and second sections when in the closed position and serves to hold the instrument module.Type: ApplicationFiled: March 15, 2006Publication date: September 20, 2007Inventors: Boon Yeap, Shiew Foo, Chee Lim, Eng Tay, Aik Ooi
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Publication number: 20070217170Abstract: An instrument module “DualPlay” housing system includes a first instrument module which is constructed from a measurement board enclosed by a first protective instrument module casing. The first instrument module is additionally enclosed in a main storage compartment of a housing. Additional instrument modules are enclosed in additional housings. Securing sections at the tops and bottoms of the housings secure the housings in a vertical stacked configuration.Type: ApplicationFiled: March 15, 2006Publication date: September 20, 2007Inventors: Boon Yeap, Shiew Foo, Chee Lim, Eng Tay, Aik Ooi