Patents by Inventor Boon Yew Low
Boon Yew Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230415397Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Patent number: 11787097Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: GrantFiled: February 10, 2021Date of Patent: October 17, 2023Assignee: NXP USA, INC.Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Patent number: 11581241Abstract: A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.Type: GrantFiled: December 29, 2020Date of Patent: February 14, 2023Assignee: NXP USA, Inc.Inventors: Boon Yew Low, Fernando A. Santos, Li Li, Fui Yee Lim, Lan Chu Tan
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Publication number: 20220250301Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.Type: ApplicationFiled: February 10, 2021Publication date: August 11, 2022Inventors: Sheila F. Chopin, Nishant Lakhera, Boon Yew Low
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Publication number: 20220208646Abstract: A circuit module (e.g., an amplifier module) includes a module substrate, a thermal dissipation structure, a semiconductor die, encapsulant material, and an interposer. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The thermal dissipation structure extends through the module substrate, and a surface of the thermal dissipation structure is exposed at the mounting surface of the module substrate. The semiconductor die is coupled to the surface of the thermal dissipation structure. The encapsulant material covers the mounting surface of the module substrate and the semiconductor die, and a surface of the encapsulant material defines a contact surface of the circuit module. The interposer is embedded within the encapsulant material. The interposer includes a conductive terminal with a proximal end coupled to a conductive pad of the module substrate, and a distal end exposed at the contact surface of the circuit module.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Inventors: Boon Yew Low, Fernando A. Santos, Li Li, Fui Yee Lim, Lan Chu Tan
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Patent number: 11056457Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.Type: GrantFiled: September 28, 2018Date of Patent: July 6, 2021Assignee: NXP USA, INC.Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong
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Publication number: 20200105709Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong
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Patent number: 9947614Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.Type: GrantFiled: March 9, 2016Date of Patent: April 17, 2018Assignee: NXP USA, Inc.Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Boon Yew Low, Akhilesh Singh
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Publication number: 20170263538Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Navas Khan ORATTI KALANDAR, Nishant LAKHERA, Boon Yew LOW, Akhilesh SINGH
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Patent number: 9418929Abstract: A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to the contact pads, and conductive threads sewn into the substrate. The conductive threads have proximal ends electrically connected to corresponding ones of the contact pads with conductive bumps. The conductive threads eliminate the need for a complicated multi-layer substrate structure for interconnect fan-out so the substrate may be formed of a variety of materials such as cloth or paper.Type: GrantFiled: April 22, 2015Date of Patent: August 16, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Boon Yew Low, Weng Hoong Chan
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Patent number: 9351407Abstract: A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.Type: GrantFiled: January 8, 2015Date of Patent: May 24, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Boon Yew Low
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Patent number: 9299675Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.Type: GrantFiled: April 16, 2015Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR,INC.Inventors: Navas Khan Oratti Kalandar, Boon Yew Low, Kesvakumar V. C. Muniandy
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Publication number: 20160071789Abstract: A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.Type: ApplicationFiled: September 8, 2014Publication date: March 10, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Pei Fan Tong, Boon Yew Low, Lan Chu Tan
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Patent number: 9190355Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.Type: GrantFiled: April 18, 2014Date of Patent: November 17, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150311143Abstract: A lead frame has a trace embedded in an encapsulant and a plurality of stubs (i) embedded in the encapsulant and (ii) connected to and extending from the trace at different locations along the length of the trace. The stubs inhibit the formation of cracks that may otherwise form along the trace due to thermal or mechanical bending of the lead frame, especially cracks that tend to occur along the four linear edge traces located at the periphery of some conventional embedded lead frames.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Boon Yew Low, Zi Song Poh
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Publication number: 20150303137Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.Type: ApplicationFiled: April 18, 2014Publication date: October 22, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar
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Patent number: 9165862Abstract: A semiconductor device package such a as Ball Grid Array (BGA), includes a die attached to a substrate. The substrate has a series of plated through holes (PTH) that include a copper pad at each of their ends. The PTH are located in a mold gate region at a corner of the substrate beyond the periphery of the die. Each PTH contains a rivet. The PTH with the pads and rivets stabilize the substrate at the mold gate region, which reduces the possibility of substrate delamination upon degating following an encapsulation process.Type: GrantFiled: September 5, 2014Date of Patent: October 20, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Boon Yew Low, Ngak Thong Teo
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Patent number: 9159682Abstract: Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.Type: GrantFiled: September 8, 2013Date of Patent: October 13, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chee Seng Foong, Boon Yew Low, Navas Khan Oratti Kalandar
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Publication number: 20150243621Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.Type: ApplicationFiled: April 16, 2015Publication date: August 27, 2015Inventors: NAVAS KHAN ORATTI KALANDAR, Boon Yew Low, Kesvakumar V.C. Muniandy
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Patent number: 9034694Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.Type: GrantFiled: February 27, 2014Date of Patent: May 19, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Navas Khan Oratti Kalandar, Boon Yew Low, Kesvakumar V. C. Muniandy