Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract: According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Abstract: According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate, where the substrate includes a high-k dielectric layer situated over the substrate and a gate electrode layer situated over the high-k dielectric layer, comprises a step of etching the gate electrode layer and the high-k dielectric layer to form a gate stack, where the gate stack comprises a high-k dielectric segment situated over the substrate and a gate electrode segment situated over the high-k dielectric segment. According to this exemplary embodiment, the method further comprises performing a nitridation process on the gate stack. The nitridation process can be performed by, for example, utilizing a plasma to nitridate sidewalls of the gate stack, where the plasma comprises nitrogen. The nitridation process can cause nitrogen to enter the high-k dielectric segment and form an oxygen diffusion barrier in the high-k dielectric segment, for example.

Abstract: A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

Abstract: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad.

Abstract: A system (30) for remotely controlling the operation of a camera (10) having a video signal tap and a lens having lens focus, zoom and T-stop adjustment motors (24, 26, 28). A digital motor driver unit (32) is connected to and controls the camera and the lens motors. A portable digital controller (34) has either a hardwire (36) or wireless connection to the motor driver unit and is sized for holding in one hand. The controller has separate controls (52, 62, 66, 70) that are manually adjustable for controlling the motor driver unit to separately and independently control the camera and the lens motors. The controller also has a display screen (56) for selectively displaying a scene from the video signal tap of the camera or data from the lens motors. The system includes a memory and processing means for selective operation with a plurality of different cameras and lenses and to calibrate the lenses to the controller and motor driver unit.

Abstract: A buried interconnect can be incorporated into the starting semiconductor on insulator wafer during the early stages of the circuit fabrication process flow for use with semiconductor devices. The buried interconnect provides an additional interconnect layer enabling an overall reduction in the silicon real estate occupied by interconnections. The buried interconnect has low resistance and can prevent the formation of unwanted PN junctions through the use of silicides. The buried interconnect and its fabrication method include an S0I wafer that has an oxidation layer formed on top of a semiconductor layer by oxidation, followed by an nitride layer formed on top of the oxide layer which then is selectively etched to form two trenches with regions of different depths. Some regions of the trenches are etched to remove all of the semiconductor layer in the trench to expose the buried oxide layer. In other regions, a thin layer of semiconductor is left at the bottom of the trenches.

Abstract: A system and method for calibrating/characterizing an electron beam (e-beam) defect inspection tool for detecting voltage contrast defects includes deliberately forming defects in a test portion of a semiconductor wafer by deliberately forming an open, short, or abnormal resistance in a circuit feature. The test portion can be in the scribe lines of a product die or on a fully populated test wafer, so that the calibration of the e-beam tool for certain inspection layers of a fabrication technology can be determined. The electron microscope output of the is checked against the known defects to determine whether the tool is accurately sensing defects.

Abstract: A system (30) for remotely controlling the operation of a camera (10) having a video signal tap and a lens having lens focus, zoom and T-stop adjustment motors (24, 26, 28). A digital motor driver unit (32) is connected to and controls the camera and the lens motors. A portable digital controller (34) has either a hardwire (36) or wireless connection to the motor driver unit and is sized for holding in one hand. The controller has separate controls (52, 62, 66, 70) that are manually adjustable for controlling the motor driver unit to separately and independently control the camera and the lens motors. The controller also has a display screen (56) for selectively displaying a scene from the video signal tap of the camera or data from the lens motors. The system includes a memory and processing means for selective operation with a plurality of different cameras and lenses and to calibrate the lenses to the controller and motor driver unit.

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad.