Patents by Inventor Boping Wu
Boping Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10763218Abstract: An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation arranged on the carrier substrate. The sidewalls of the electromagnetic shielding encapsulation laterally surround the at least one electrical component. Further, the electrical device includes a heat sink mounted to the sidewalls of the electromagnetic shielding encapsulation. The heat sink forms a cap of the electromagnetic shielding encapsulation and the heat sink includes surface-enlarging structures at a front side of the heat sink.Type: GrantFiled: March 24, 2016Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Sruti Chigullapalli, Leslie Fitch, Boping Wu
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Publication number: 20190074252Abstract: An electrical device includes at least one electrical component arranged on a carrier substrate and sidewalls of an electromagnetic shielding encapsulation arranged on the carrier substrate. The sidewalls of the electromagnetic shielding encapsulation laterally surround the at least one electrical component. Further, the electrical device includes a heat sink mounted to the sidewalls of the electromagnetic shielding encapsulation. The heat sink forms a cap of the electromagnetic shielding encapsulation and the heat sink includes surface-enlarging structures at a front side of the heat sink.Type: ApplicationFiled: March 24, 2016Publication date: March 7, 2019Inventors: Sruti Chigullapalli, Leslie Fitch, Boping Wu
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Publication number: 20180270948Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: August 14, 2017Publication date: September 20, 2018Applicant: Intel CorporationInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Patent number: 10015878Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: November 19, 2015Date of Patent: July 3, 2018Assignee: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Patent number: 9750129Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 14, 2016Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Publication number: 20170006698Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Patent number: 9485854Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: GrantFiled: August 20, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Publication number: 20160309580Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: November 19, 2015Publication date: October 20, 2016Applicant: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Publication number: 20160057851Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Patent number: 9225164Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: November 6, 2014Date of Patent: December 29, 2015Assignee: INTEL CORPORATIONInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Publication number: 20150131190Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Patent number: 8913364Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: GrantFiled: December 20, 2011Date of Patent: December 16, 2014Assignee: Intel CorporationInventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Publication number: 20130157482Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Inventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
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Patent number: 7649265Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2006Date of Patent: January 19, 2010Assignee: Intel CorporationInventors: Chunfei Ye, Boping Wu
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Publication number: 20080079139Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Chunfei Ye, Boping Wu