Patents by Inventor Bor-Cheng Chen

Bor-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6929965
    Abstract: A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET's.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: August 16, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Cheng Chen, Yu-Feng Tai
  • Publication number: 20030194822
    Abstract: A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET's.
    Type: Application
    Filed: June 16, 2003
    Publication date: October 16, 2003
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Bor-Cheng Chen, Yu-Feng Tai
  • Patent number: 6593157
    Abstract: A method of early and effective detection of plasma damage to a gate oxide layer by a special design of the active region is achieved. A plasma-damage testing structure is fabricated by providing a gate electrode overlying an active area of a semiconductor substrate wherein a gate oxide layer underlies the gate electrode. A portion of the active area underlying the gate electrode has sharp corners. The plasma-damage testing structure is exposed to a plasma environment. Electrical tests are performed to detect plasma damage to the plasma-damage testing structure. This model provides an accurate evaluation of plasma damage to actual MOSFET's.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: July 15, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bor-Cheng Chen, Yu-Feng Tai
  • Patent number: 6258706
    Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: July 10, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ho-Yin Yiu, Lin-June Wu, Bor-Cheng Chen, J. H. Horng
  • Patent number: 5942800
    Abstract: A method for forming a chess-board patterned bond pad structure with stress buffered characteristics and the bond pad structure formed are disclosed. In one method, a multiplicity of field oxide regions are first formed in the surface of a silicon substrate. A conductive layer such as polycide is then deposited and formed on the substrate to form a stepped surface with a metal layer subsequently deposited on top of the conductive layer to form a bond pad. The stepped structure reproduced on the metal layer serves to distribute bonding stresses during a wire bonding process such that bond pad lift-off defects are substantially eliminated. In another method, the conductive layer is first formed into conductive gates with insulating sidewalls formed subsequently. Similarly stepped surface on a metal layer can be obtained to realize the stress buffered characteristics of the novel method.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: August 24, 1999
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ho-Yin Yiu, Lin-June Wu, Bor-Cheng Chen, Jan-Her Horng
  • Patent number: 5745239
    Abstract: An apparatus and method of analyzing particles on an integrated circuit wafer using a quasi three dimensional image analysis of the particles. The apparatus includes an optical system which has an optical axis and forms an image of that part of a focal plane which within a field distance of the optical axis. The apparatus holds a wafer perpendicular to the optical axis and allows the surface of the wafer to be moved in a plane perpendicular to the optical axes to view the entire surface of the wafer. The apparatus also allows the surface of the wafer to be moved a step distance below the focal plane. Images formed at a number of step distances are used to form a quasi three dimensional image of particles on the surface of the wafer. Automatic image analysis is used when appropriate.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: April 28, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bor-Cheng Chen, Yeh-Jye Wann