Patents by Inventor Bor-Doou Rong
Bor-Doou Rong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420028Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: ApplicationFiled: September 1, 2023Publication date: December 28, 2023Applicant: ETRON TECHNOLOGY, INC.Inventors: Chao-Chun LU, Bor-Doou RONG, Chun SHIAH
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Patent number: 11798613Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: GrantFiled: April 7, 2021Date of Patent: October 24, 2023Assignee: ETRON TECHNOLOGY, INC.Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
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Publication number: 20220246192Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.Type: ApplicationFiled: January 12, 2022Publication date: August 4, 2022Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Chun Shiah, Bor-Doou Rong
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Publication number: 20220246199Abstract: The present invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word line coupled to a gate terminal of the access transistor. During the period between the word line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: ApplicationFiled: April 10, 2022Publication date: August 4, 2022Applicants: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Chun Shiah, Bor-Doou Rong
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Patent number: 11302383Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: GrantFiled: March 15, 2019Date of Patent: April 12, 2022Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
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Publication number: 20210295893Abstract: This invention discloses sustainable DRAM with principle power supply voltage which is unified with an external logic circuit. The DRAM circuit is configured to couple with the external logic circuit and with a principle power supply voltage source. The DRAM circuit comprises a first sustaining voltage generator and a DRAM core circuit. The first sustaining voltage generator generates a first voltage level which is higher than a voltage level corresponding to a signal ONE utilized in the DRAM circuit. The DRAM core circuit has a DRAM cell comprising an access transistor and a storage capacitor, and the storage capacitor of the DRAM cell is configured to selectively coupled to the first sustaining voltage generator. Wherein, a voltage level of the principle power supply voltage source to the DRAM circuit is the same or substantially the same as that of a principle power supply voltage source to the external logic circuit.Type: ApplicationFiled: May 28, 2021Publication date: September 23, 2021Applicant: ETRON TECHNOLOGY, INC.Inventors: Chao-Chun LU, Bor-Doou RONG, Chun SHIAH
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Publication number: 20210225434Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Applicant: ETRON TECHNOLOGY, INC.Inventors: Chao-Chun LU, Bor-Doou RONG, Chun SHIAH
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Publication number: 20200185022Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.Type: ApplicationFiled: March 15, 2019Publication date: June 11, 2020Inventors: Chao-Chun Lu, Bor-Doou Rong, Chun Shiah
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Patent number: 9601456Abstract: A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads. The bundled memory includes a first memory die and a second memory die side-by-side formed over a substrate, wherein the first memory die includes a first group of pads and the second memory die includes a second group of pads. The encapsulation package material encloses the non-memory chip and the bundled memory, and the non-memory chip is electronically coupling with the bundled memory through the plurality of pads, the first and the second group of pads. The first group of pads corresponds to the second group of pads by rotating a predetermined degree or by mirror mapping.Type: GrantFiled: January 19, 2015Date of Patent: March 21, 2017Assignee: Etron Technology, Inc.Inventors: Bor-Doou Rong, Weng-Dah Ken
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Patent number: 9589931Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: GrantFiled: April 27, 2015Date of Patent: March 7, 2017Assignee: Etron Technology, Inc.Inventors: Bor-Doou Rong, Chun Shiah
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Patent number: 9465430Abstract: A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage.Type: GrantFiled: May 23, 2014Date of Patent: October 11, 2016Assignees: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, ETRON TECHNOLOGY, INC.Inventors: Chun Shiah, Bor-Doou Rong
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Patent number: 9214448Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: GrantFiled: June 25, 2014Date of Patent: December 15, 2015Assignee: Etron Technology, Inc.Inventors: Bor-Doou Rong, Chun Shiah
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Publication number: 20150228620Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Bor-Doou Rong, Chun Shiah
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Publication number: 20150206849Abstract: A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads. The bundled memory includes a first memory die and a second memory die side-by-side formed over a substrate, wherein the first memory die includes a first group of pads and the second memory die includes a second group of pads. The encapsulation package material encloses the non-memory chip and the bundled memory, and the non-memory chip is electronically coupling with the bundled memory through the plurality of pads, the first and the second group of pads. The first group of pads corresponds to the second group of pads by rotating a predetermined degree or by mirror mapping.Type: ApplicationFiled: January 19, 2015Publication date: July 23, 2015Inventors: Bor-Doou Rong, Weng-Dah Ken
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Patent number: 9070558Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: GrantFiled: March 13, 2013Date of Patent: June 30, 2015Assignee: Etron Technology, Inc.Inventors: Bor-Doou Rong, Chun Shiah
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Publication number: 20140351609Abstract: A memory with variable operation voltage is disclosed. The disclosed DRAM comprises a core memory module, a register, and a first voltage adjustment module. The core memory module operates with a first control voltage. The register is used for storing a plurality of control signals and selecting one among the control signals as a voltage control signal according to an input signal. The first voltage adjustment module is respectively electrically connected to the register, the core memory module, and an external voltage, so as to provide the first control voltage according to the voltage control signal and the external voltage.Type: ApplicationFiled: May 23, 2014Publication date: November 27, 2014Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, Etron Technology, Inc.Inventors: Chun SHIAH, Bor-Doou RONG
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Publication number: 20140308809Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Inventors: Bor-Doou Rong, Chun Shiah
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Publication number: 20130248860Abstract: A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus.Type: ApplicationFiled: March 13, 2013Publication date: September 26, 2013Applicant: ETRON TECHNOLOGY, INC.Inventors: Bor-Doou Rong, Chun Shiah
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Patent number: 7983102Abstract: A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.Type: GrantFiled: October 15, 2009Date of Patent: July 19, 2011Assignee: Etron Technology, Inc.Inventors: Shih-Hsing Wang, Der-Min Yuan, Bor-Doou Rong, Chun Shiah
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Publication number: 20100103753Abstract: A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.Type: ApplicationFiled: October 15, 2009Publication date: April 29, 2010Inventors: Shih-Hsing WANG, Der-Min Yuan, Bor-Doou Rong, Chun Shiah